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AD7865AS-1-AD7865AS-3-AD7865BS-1
Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC
REV.A
Four-Channel, Simultaneous
Sampling, Fast, 14-Bit ADC
FEATURES
Fast (2.4␣ms) 14-Bit ADC
Four Simultaneously Sampled Inputs
Four Track/Hold Amplifiers
0.35␣ms Track/Hold Acquisition Time
2.4 ms Conversion Time per Channel
HW/SW Select of Channel Sequence for Conversion
Single Supply Operation
Selection of Input Ranges: 610 V, 65 V and 62.5 V,
0 V to +5 V and 0 V to +2.5 V
High Speed Parallel Interface Which Also Allows
Interfacing to 3 V Processors
Low Power, 115 mW Typ
Power Saving Mode, 15␣mW Typ
Overvoltage Protection on Analog Inputs
APPLICATIONS
AC Motor Control
Uninterruptible Power Supplies
Industrial Power Meters/Monitors
Data Acquisition Systems
Communications
GENERAL DESCRIPTIONThe AD7865 is a fast, low power, four-channel simultaneous
sampling 14-bit A/D converter that operates from a single +5␣V
supply. The part contains a 2.4 ms successive approximation
ADC, four track/hold amplifiers, 2.5 V reference, on-chip clock
oscillator, signal conditioning circuitry and a high speed parallel
interface. The input signals on four channels are sampled simul-
taneously thus preserving the relative phase information of the
signals on the four analog inputs. The part accepts analog input
ranges of –10␣V, –5 V, –2.5 V, 0 V to +2.5 V and 0 V to +5 V.
The part allows any subset of the four channels to be converted
in order to maximize the throughput rate on the selected se-
quence. The channels to be converted can be selected either via
hardware (channel select input pins) or via software (program-
ming the channel select register).
A single conversion start signal (CONVST) simultaneously places
all the track/holds into hold and initiates conversion sequence
for the selected channels. The EOC signal indicates the end of
each individual conversion in the selected conversion sequence.
The BUSY signal indicates the end of the conversion sequence.
Data is read from the part via a 14-bit parallel data bus using the
standard CS and RD signals. Maximum throughput for a single
channel is 350 kSPS. For all four channels the maximum through-
put is 100 kSPS.
The AD7865 is available in a small (0.3 sq. inch area) 44-lead
PQFP.
PRODUCT HIGHLIGHTS1. The AD7865 features four Track/Hold amplifiers and a fast
(2.4 ms) ADC allowing simultaneous sampling and then
conversion of any subset of the four channels.
2. The AD7865 operates from a single +5␣V supply and con-
sumes only 115 mW typ, making it ideal for low power and
portable applications.
3. The part offers a high speed parallel interface for easy con-
nection to microprocessors, microcontrollers and digital
signal processors.
4. The part is offered in three versions with different analog
input ranges. The AD7865-1 offers the standard industrial
ranges of –10 V and –5 V; the AD7865-2 offers a unipolar
range of 0 V to +2.5 V or 0 V to +5 V and the AD7865-3
offers the common signal processing input range of –2.5 V.
5. The part features very tight aperture delay matching between
the four input sample and hold amplifiers.
FUNCTIONAL BLOCK DIAGRAM
AD7865–SPECIFICATIONS
(VDD = +5 V 6 5%, AGND = DGND = 0 V, VREF = Internal. Clock = Internal; all specifi-
cations TMIN to TMAX unless otherwise noted.)
AD7865LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION RATE
POWER REQUIREMENTS
NOTESTemperature ranges are as follows : A, B Versions: –40°C to +85°C, Y Version: –40°C to +105°C.Performance measured through full channel (SHA and ADC).See Terminology.Total Harmonic Distortion and Peak Harmonic or Spurious Noise are specified at –83 dBs for the AD7865-2.
AD7865
TIMING CHARACTERISTICS1, 2tACQ
tBUSY
tWAKE-UP—External VREF
Write Operation
External Clock
NOTESSample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6␣V.See Figures 6, 7 and 8.Refer to the Standby Mode Operation section. The MAX specification of 1 ms is valid when using a 0.1 mF decoupling capacitor on the VREF pin.Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8␣V or 2.4 V.These times are derived from the measured time taken by the data outputs to change 0.5␣V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
TO OUTPUT
PIN+1.6VFigure 1.Load Circuit for Access Time and Bus Relinquish Time
(VDD = +5 V 6 5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifications
TMIN to TMAX unless otherwise noted.)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7865 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
VDRIVE to DGND . . . . . . . . . . . . . . . . . . . . . . . . .VDD + 0.3 V
Analog Input Voltage to AGND
AD7865-1 (–10 V Input Range) . . . . . . . . . . . . . . . .–18 V
AD7865-1 (–5 V Input Range) . . . . . . . . . . . . . . . . . .–9 V
AD7865-2 . . . . . . . . . . . . . . . . . . . . . . . . . . .–1 V to +18 V
AD7865-3 . . . . . . . . . . . . . . . . . . . . . . . . . . .–4 V to +18 V
Reference Input Voltage to AGND . . . .–0.3 V to VDD + 0.3␣V
Digital Input Voltage to DGND . . . . . .–0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . .–40°C to +85°C
Automotive (Y Version) . . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
PQFP Package, Power Dissipation . . . . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
PIN CONFIGURATION
AD7865
PIN FUNCTION DESCRIPTIONS18–21
38, 39
40–43
AD7865
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 14-bit converter, this is 86.04␣dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7865 it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4 and V5 are the rms amplitudes of the second through the fifth
harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
The AD7865 is tested using two input frequencies. In this case,
the second and third order terms are of different significance.
The second order terms are usually distanced in frequency from
the original sine waves, while the third order terms are usually at
a frequency close to the input frequencies. As a result, the sec-
ond and third order terms are specified separately. The calcula-
tion of the intermodulation distortion is as per the THD speci-
fication where it is the ratio of the rms sum of the individual
distortion products to the rms amplitude of the fundamental
expressed in dBs.
Channel-to-Channel IsolationChannel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 10␣kHz sine wave signal to one channel and a 50 kHz
signal to another channel and measuring how much of that
signal is coupled onto the first channel. The figure given is the
worst case across all four channels of the AD7865.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the idealLSB change between any two adjacent codes in the ADC.
Positive Gain Error (AD7865-1, AD7865-3)This is the deviation of the last code transition (01...110 to...111) from the ideal 4 · VREF – 3/2 LSB (AD7865 at10 V), 2 · VREF – 3/2 LSB (AD7865 at –5 V range) or
VREF – 3/2 LSB (AD7865 at –2.5 V range), after the Bipolar
Offset Error has been adjusted out.
Positive Gain Error (AD7865-2)This is the deviation of the last code transition (111...110 to
111...111) from the ideal 2 · VREF – 3/2 LSB (AD7865 at
0 V to +5 V), VREF – 3/2 LSB (AD7865 at 0 V to +2.5 V)
after the Unipolar Offset Error has been adjusted out.
Unipolar Offset Error (AD7865-2)This is the deviation of the first code transition (000...000 to
000...001) from the ideal AGND + 1/2 LSB.
Bipolar Zero Error (AD7865-1, AD7865-3)This is the deviation of the midscale transition (all 0s to 1s)
from the ideal AGND – 1/2 LSB.
Negative Gain Error (AD7865-1, AD7865-3)This is the deviation of the first code transition (10...000 to...001) from the ideal –4 · VREF + 1/2 LSB (AD7865 at10 V), –2 · VREF + 1/2 LSB (AD7865 at –5 V range) or
–VREF + 1/2 LSB (AD7865 at –2.5 V range), after Bipolar Zero
Error has been adjusted out.
Track/Hold Acquisition TimeTrack/Hold acquisition time is the time required for the out-
put of the track/hold amplifier to reach its final value, within1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the selected VINxA/VINxB input of the AD7865. It means that
the user must wait for the duration of the track/hold acquisition
time after the end of conversion or after a step input change to
VINxA/VINxB before starting another conversion, to ensure that
the part operates to specification.
CONVERTER DETAILSThe AD7865 is a high speed, low power, four-channel simulta-
neous sampling 14-bit A/D converter that operates from a single
+5␣V supply. The part contains a 2.4␣ms successive approxima-
tion ADC, four track/hold amplifiers, an internal +2.5␣V refer-
ence and a high speed parallel interface. There are four analog
inputs which can be sampled simultaneously, thus preserving
the relative phase information of the signals on all four analog
inputs. Thereafter, conversions will be completed on the se-
lected subset of the four channels. The part accepts an analog
input range of –10 V or –5 V (AD7865-1), 0 V to +2.5 V orV to +5V (AD7865-2) and –2.5 V (AD7865-3). Overvoltage
protection on the analog inputs for the part allows the input
voltage to go to –18 V (AD7865-1 with –10 V input range), –9V
(AD7865-1 with –5V input range), –1V to +18 V (AD7865-2)
and –4 V to +18 V (AD7865-3) without causing damage or effect-
ing the conversion result of another channel. The AD7865 has
two operating modes Reading Between Conversions and Reading
after the Conversion Sequence. These modes are discussed in more
detail in the Timing and Control section.
A conversion is initiated on the AD7865 by pulsing the CONVST
input. On the rising edge of CONVST, all four on-chip track/
holds are simultaneously placed into hold and the conversion
sequence is started on all the selected channels. Channel selec-
tion is made via the SL1–SL4 pins if H/S SEL is logic zero, or
via the channel select register if H/S SEL is logic one—see
Selecting a Conversion Sequence. The channel select register is
programmed via the bidirectional data lines DB0–DB3 and a
standard write operation. The selected conversion sequence is
latched on the rising edge of CONVST so changing a selection
will only take effect once a new conversion sequence is initiated.
The BUSY output signal is triggered high on the rising edge ofCONVST and will remain high for the duration of the conver-
sion sequence. The conversion clock for the part is generated
internally using a laser-trimmed clock oscillator circuit. There is
also the option of using an external clock, by tying the INT/
EXT CLK pin logic high and applying an external clock to the
CLKIN pin. However, the optimum throughput is obtained by
using the internally generated clock— see Using an External
Clock. The EOC signal indicates the end of each conversion in the
conversion sequence. The BUSY signal indicates the end of the
full conversion sequence and at this time all four Track and Holds
return to tracking mode. The conversion results can either be read
at the end of the full conversion sequence (indicated by BUSY
going low) or as each result becomes available (indicated by EOC
going low). Data is read from the part via a 14-bit parallel data bus
with standard CS and RD signals—see Timing and Control.
Conversion time for each channel of the AD7865 is 2.4 ms and
the track/hold acquisition time is 0.35ms. To obtain optimum
performance from the part, the read operation should not occur
during a channel conversion or during the 100 ns prior to the
next CONVST rising edge. This allows the part to operate at
throughput rates up to 100 kHz for all four channels and achieve
data sheet specifications.
Track/Hold SectionThe track/hold amplifiers on the AD7865 allows the ADCs to
accurately convert an input sine wave of full-scale amplitude to
The track/hold amplifiers acquire input signals to 14-bit accu-
racy in less than 350 ns. The operation of the track/holds are
essentially transparent to the user. The four track/hold amplifi-
ers sample their respective input channels simultaneously, on
the rising edge of CONVST. The aperture time for the track/
holds (i.e., the delay time between the external CONVST signal
and the track/hold actually going into hold) are typically 15␣ns
and, more importantly, is well matched across the four track/
holds on one device and also well matched from device to de-
vice. This allows the relative phase information between differ-
ent input channels to be accurately preserved. It also allows
multiple AD7865s to sample more than four channels simulta-
neously. At the end of a conversion sequence, the part returns
to its tracking mode. The acquisition time of the track/hold
amplifiers begins at this point.
The autozero section of the track/hold circuit is designed to
work with input slew rates of up to 4 · p · (Full-Scale Span).
This corresponds to a full-scale sine wave of up to 4 MHz for
any input range. Slew rates above this level within the acquisi-
tion time may cause an incorrect conversion result to be re-
turned from the AD7865.
Reference SectionThe AD7865 contains a single reference pin, labelled VREF,
which either provides access to the part’s own +2.5␣V reference
or allows an external +2.5␣V reference to be connected to pro-
vide the reference source for the part. The part is specified with
a +2.5␣V reference voltage.
The AD7865 contains an on-chip +2.5␣V reference. To use this
reference as the reference source for the AD7865, simply con-
nect a 0.1␣mF disc ceramic capacitor from the VREF pin to AGND.
The voltage that appears at this pin is internally buffered before
being applied to the ADC. If this reference is required for use
external to the AD7865, it should be buffered as the part has a
FET switch in series with the reference output, resulting in a
source impedance for this output of 6 kW nominal. The toler-
ance on the internal reference is –10␣mV at +25°C with a typi-
cal temperature coefficient of 25␣ppm/°C and a maximum error
over temperature of –20 mV.
If the application requires a reference with a tighter tolerance or
the AD7865 needs to be used with a system reference, the user
has the option of connecting an external reference to this VREF
pin. The external reference will effectively overdrive the internal
reference and thus provide the reference source for the ADC.
The reference input is buffered before being applied to the ADC
with the maximum input current of –100␣mA. Suitable reference
sources for the AD7865 include the AD680, AD780, REF192
and REF43 precision +2.5␣V references.
CIRCUIT DESCRIPTION
Analog Input SectionThe AD7865 is offered as three part types, the AD7865-1 where
each input can be configured for –10 V or a –5 V input voltage
range, the AD7865-3 which handles input voltage range –2.5 V
and the AD7865-2 which has an input voltage range of 0 V to
+2.5 V or 0 V to +5 V. The amount of current flowing into the
analog input will depend on the analog input range and the analog
AD7865
AD7865-1Figure 2 shows the analog input section of the AD7865-1. Each
input can be configured for –5 V or –10 V operation on the
AD7865-1. For –5 V operation, the VINxA and VINxB inputs are
tied together and the input voltage is applied to both. For –10 V
operation, the VINxB input is tied to AGND and the input volt-
age is applied to the VINxA input. The VINxA and VINxB inputs are
symmetrical and fully interchangeable. Thus for ease of PCB
layout on the –10 V range, the input voltage may be applied to
the VINxB input while the VINxA input is tied to AGND.
VINxA
GND
VINxB
VREFFigure 2.AD7865-1 Analog Input Structure
For the AD7865-1, R1 = 4 kW, R2 = 16 kW, R3 = 16 kW and
R4 = 8 kW. The resistor input stage is followed by the high
input impedance stage of the track/hold amplifier.
The designed code transitions take place midway between suc-
cessive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs
etc.) LSB size is given by the formula, 1 LSB = FSR/16384. For
the –5 V range, 1 LSB = 10 V/16384 = 610.4 mV. For the –10 V
range, 1 LSB = 20 V/16384 = 1.22 mV. Output coding is twos
complement binary with 1 LSB = FSR/16384. The ideal input/
output transfer function for the AD7865-1 is shown in Table I.
Table I.Ideal Input/Output Code Table for the AD7865-1NOTESFSR is full-scale range and is 20 V for the –10 V range and 10 V for the –5 V
range, with VREF = +2.5 V.1 LSB = FSR/16384 = 1.22 mV (–10 V—AD7865-1) and 610.4 mV (–5 V—
AD7865-1) with VREF = +2.5 V.
AD7865-2Figure 3 shows the analog input section of the AD7865-2. Each
input can be configured for 0 V to +5 V operation or 0 V to +2.5 V
operation. For the 0 V to +5 V operation, the VINxB input is tied
to AGND and the input voltage is applied to VINxA input. For
0 V to +2.5 V operation, the VINxA and VINxB inputs are tied
together and the input voltage is applied to both. The VINxA and
VINxB inputs are symmetrical and fully interchangeable. Thus for
ease of PCB layout on the 0 V to +5 V range the input voltage
may be applied to the VINxB input while the VINxA input is tied to
AGND.
For the AD7865-2, R1 = 4 kW and R2 = 4 kW. Once again, the
designed code transitions occur on successive integer LSB val-
ues. Output coding is straight (natural) binary with 1 LSB =
FSR/16384 = +2.5 V/16384 = 0.153 mV, and +5 V/16384 =
0.305 mV, for 0 V to +2.5 V and 0 V to +5 V options respec-
tively. Table II shows the ideal input and output transfer
function for the AD7865-2.
VINxA
VINxB
VREFFigure 3.AD7865-2 Analog Input Structure
Table II.Ideal Input/Output Code Table for the AD7865-2NOTESFSR is full-scale range and is 0 V to +2.5 V and 0 V to +5 V for AD7865-2
with VREF = +2.5 V.1 LSB = FSR/16384 and is 0.153 mV (0 V to +2.5 V) and 0.305 mV (0 V to +5 V)
for AD7865-2) with VREF = +2.5 V.
