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ADM2490EBRWZ , High Speed, ESD-Protected, Full-Duplex, iCoupler, Isolated RS-485 Transceiver
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AD7864AS-1-AD7864AS-2-AD7864AS-3
4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC
REV.A
4-Channel, Simultaneous
Sampling, High Speed, 12-Bit ADC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High Speed (1.65␣ms) 12-Bit ADC
Four Simultaneously Sampled Inputs
Four Track/Hold Amplifiers
0.35␣ms Track/Hold Acquisition Time
1.65 ms Conversion Time per Channel
HW/SW Select of Channel Sequence for Conversion
Single Supply Operation
Selection of Input Ranges:610 V, 65 V for AD7864-1
62.5 V for AD7864-3
0 V to 2.5 V, 0 V to 5 V for AD7864-2
High Speed Parallel Interface Which Also Allows
Interfacing to 3 V Processors
Low Power, 90 mW Typ
Power Saving Mode, 20␣mW Typ
Overvoltage Protection on Analog Inputs
APPLICATIONS
AC Motor Control
Uninterrupted Power Supplies
Data Acquisition Systems
Communications
GENERAL DESCRIPTIONThe AD7864 is a high speed, low power, 4-channel simulta-
neous sampling 12-bit A/D converter that operates from a single
+5␣V supply. The part contains a 1.65 ms successive approxima-
tion ADC, four track/hold amplifiers, 2.5 V reference, on-chip
clock oscillator, signal conditioning circuitry and a high speed
parallel interface. The input signals on four channels are
sampled simultaneously, thus preserving the relative phase infor-
mation of the signals on the four analog inputs. The part accepts
analog input ranges of –10␣V, –5 V (AD7864-1), 0 V to 2.5 V,
0 V to 5 V for AD7864-2 and –2.5␣V (AD7864-3).
The part allows any subset of the four channels to be converted
in order to maximize the throughput rate on the selected se-
quence. The channels to be converted can be selected via either
hardware (channel select input pins) or software (programming
the channel select register).
A single conversion start signal (CONVST) simultaneously
places all the track/holds into hold and initiates conversion se-
quence for the selected channels. The EOC signal indicates the end
of each individual conversion in the selected conversion sequence.
The BUSY signal indicates the end of the conversion sequence.
Data is read from the part by means of a 12-bit parallel data
bus using the standard CS and RD signals. Maximum through-
put for a single channel is 500 kSPS. For all four channels the
maximum throughput is 130 kSPS for the read during conver-
sion sequence operation. The throughput rate for the read after
conversion sequence operation will depend on the read cycle
time of the processor. See Timing and Control section.
The AD7864 is available in a small (0.3 sq. inch area) 44-lead
MQFP.
PRODUCT HIGHLIGHTSThe AD7864 features four Track/Hold amplifiers and a fast
(1.65 ms) ADC allowing simultaneous sampling and then
conversion of any subset of the four channels.The AD7864 operates from a single +5␣V supply and consumes
only 90 mW typ making it ideal for low power and portable
applications. Also see Standby Mode Operation.The part offers a high speed parallel interface for easy con-
nection to microprocessors, microcontrollers and digital
signal processors.The part is offered in three versions with different analog
input ranges. The AD7864-1 offers the standard industrial
input ranges of –10 V and –5 V; the AD7864-3 offers the
common signal processing input range of –2.5 V; the
AD7864-2 can be used in unipolar 0 V to 2.5 V, 0 V to 5 V
applications.The part features very tight aperture delay matching between
the four input sample-and-hold amplifiers.
AD7864–SPECIFICATIONS
(VDD = +5 V 6 5%, AGND = DGND = 0 V, VREF = Internal. Clock = Internal; all specifi-
cations TMIN to TMAX unless otherwise noted.)SAMPLE AND HOLD
ANALOG INPUTS
AD7864LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION RATE
POWER REQUIREMENTS
NOTESTemperature ranges are as follows: A, B Versions: –40°C to +85°C. Note: The A Version is fully specified up to +105°C with degraded INL and DNL specifications
of –2 LSBs max.Performance measured through full channel (SHA and ADC).See Terminology.Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
AD7864
TIMING CHARACTERISTICS1, 2tACQ
tBUSY
t10
t11
Write Operation
t13
t14
t15
t16
NOTESSample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6␣V.See Figures 7, 8 and 9.Refer to the Standby Mode Operation section. The MAX specification of 6 ms is valid when using a 0.1 mF decoupling capacitor on the VREF pin.Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8␣V or 2.4 V.These times are derived from the measured time taken by the data outputs to change 0.5␣V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
(VD = +5 V 6 5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifications
TMIN to TMAX unless otherwise noted.)Figure 1.Load Circuit for Access Time and Bus Relinquish Time
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7864 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
Analog Input Voltage to AGND
AD7864-1 (–10 V Input Range) . . . . . . . . . . . . . . . .–20 V
AD7864-1 (–5 V Input Range) . . . . . . . . . . .–7 V to +20 V
AD7864-3 . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V to +20 V
AD7864-2 . . . . . . . . . . . . . . . . . . . . . . . . . . .–1 V to +20 V
Reference Input Voltage to AGND . . .–0.3 V to VDD + 0.3␣V
Digital Input Voltage to DGND . . . . .–0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
MQFP Package, Power Dissipation . . . . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE*The A Version is fully specified up to +105°C with degraded INL and DNL specifications of –2 LSBs max.
PIN CONFIGURATION
DB7
DB8
DB9
DB10
DB11
CLKIN
INT/EXT CLK
BUSY
FRSTDATA
CONVST
SL1
SL2
SL3
SL4
H/S SEL
AGND
AVDD
VREF
VREFGND
IN2A
IN1B
IN1A
STBY
EOCDB0DB1DB3DB4DB5DGND
AGND
DRIVE
IN4B
IN2B
DB2
AGND
IN4A
DB6
IN3B
IN3A
AD7864
PIN FUNCTION DESCRIPTION29–34
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74␣dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7864 it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4 and V5 are the rms amplitudes of the second through the fifth
harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
The AD7864 is tested using the CCIF standard, where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of differ-
ent significance. The second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Channel-to-Channel IsolationChannel-to-Channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 50␣kHz sine wave signal to all nonselected input channels
and determining how much that signal is attenuated in the
selected channel. The figure given is the worst case across all four
channels.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the idealLSB change between any two adjacent codes in the ADC.
Positive Full-Scale ErrorThis is the deviation of the last code transition (01...110 to...111) from the ideal 4 · VREF – 3/2 LSB (AD7864-110 V), 2 · VREF – 3/2 LSB (AD7864-1 –5 V range) or VREF
– 3/2 LSB (AD7864-3, –2.5 V range), after the Bipolar Offset
Error has been adjusted out.
Positive Full-Scale Error (AD7864-2, 0 V to 2.5 V and 0 V to
5 V)This is the deviation of the last code transition (11...110 to...111) from the ideal 2 · VREF – 3/2 LSB (AD7864-2 0 V
to 5 V range), or VREF – 3/2 LSB (AD7864-2 0 V to 2.5 V
range), after the Unipolar Offset Error has been adjusted out.
Bipolar Zero Error (AD7864-1, 610/65 V, AD7864-3 , 62.5 V)This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AGND – 1/2 LSB.
Unipolar Offset Error (AD7864-2, 0 V to 2.5 V and 0 V to 5 V)This is the deviation of the first code transition (00...000 to...001) from the ideal AGND + 1/2 LSB.
Negative Full-Scale Error (AD7864-1, 610/65 V, AD7864-3,62.5 V)
This is the deviation of the first code transition (10...000 to...001) from the ideal –4 · VREF + 1/2 LSB (AD7864-110 V), –2 · VREF + 1/2 LSB (AD7864-1 –5 V range) or
–VREF + 1/2 LSB (AD7864-3, –2.5 V range), after Bipolar
Zero Error has been adjusted out.
Track/Hold Acquisition TimeTrack/Hold acquisition time is the time required for the out-
put of the track/hold amplifier to reach its final value, within1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the selected VINXA/VINXB input of the AD7864. It means that
the user must wait for the duration of the track/hold acquisition
time after the end of conversion or after a step input change to
VINXA/VINXB before starting another conversion, to ensure that
the part operates to specification.
AD7864
CONVERTER DETAILSThe AD7864 is a high speed, low power, 4-channel simulta-
neous sampling 12-bit A/D converter that operates from a single
+5␣V supply. The part contains a 1.65␣ms successive approxima-
tion ADC, four track/hold amplifiers, an internal +2.5␣V refer-
ence and a high speed parallel interface. There are four analog
inputs that can be simultaneously sampled thus preserving the
relative phase information of the signals on all four analog in-
puts. Thereafter, conversions will be completed on the selected
subset of the four channels. The part accepts an analog input
range of –10␣V or –5␣V (AD7864-1), –2.5␣V (AD7864-3) and
0 V–2.5 V or 0 V–5 V (AD7864-2). Overvoltage protection on
the analog inputs of the part allows the input voltage to go to20 V, (AD7864-1 –10 V range), –7 V or +20 V (AD7864-15 V range) –1 V to +20 V (AD7864-2) and –7 V to +20 V
(AD7864-3) without causing damage or effecting a conversion in
progress. The AD7864 has two operating modes Reading Between
Conversions and Reading after the Conversion Sequence. These
modes are discussed in more detail in the Timing and Control
section.
A conversion is initiated on the AD7864 by pulsing the CONVST
input. On the rising edge of CONVST, all four on-chip track/
holds are placed into hold simultaneously and the conversion
sequence is started on all the selected channels. Channel
selection is made via the SL1–SL4 pins if H/S SEL is logic zero
or via the channel select register if H/S SEL is logic one—see
Selecting a Conversion Sequence. The channel select register is
programmed via the bidirectional data lines DB0–DB3 and a
standard write operation. The selected conversion sequence is
latched on the rising edge of CONVST so changing a selection
will only take effect once a new conversion sequence is initiated.
The BUSY output signal is triggered high on the rising edge ofCONVST and will remain high for the duration of the conver-
sion sequence. The conversion clock for the part is generated
internally using a laser-trimmed clock oscillator circuit. There is
also the option of using an external clock, by tying the INT/
EXT CLK pin logic high, and applying an external clock to the
CLKIN pin. However, the optimum throughput is obtained by
using the internally generated clock—see Using an External
Clock. The EOC signal indicates the end of each conversion in
the conversion sequence. The BUSY signal indicates the end of
the full conversion sequence and at this time all four Track and
Holds return to tracking mode. The conversion results can
either be read at the end of the full conversion sequence
(indicated by BUSY going low) or as each result becomes
available (indicated by EOC going low). Data is read from the
part via a 12-bit parallel data bus with standard CS and RD
signals—see Timing and Control.
Conversion time for each channel of the AD7864 is 1.65 ms and
the track/hold acquisition time is 0.35ms. To obtain optimum
performance from the part, the read operation should not occur
during a channel conversion or during the 100 ns prior to the
next CONVST rising edge. This allows the part to operate at
throughput rates up to 130 kHz for all four channels and
achieve data sheet specifications.
Track/Hold SectionThe track/hold amplifiers on the AD7864 allows the ADCs to
accurately convert an input sine wave of full-scale amplitude to
12-bit accuracy. The input bandwidth of the track/hold is greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate of 500 kSPS (i.e., the
track/hold can handle input frequencies in excess of 250␣kHz).
The track/hold amplifiers acquire input signals to 12-bit accu-
racy in less than 350␣ns. The operation of the track/holds are
essentially transparent to the user. The four track/hold amplifi-
ers sample their respective input channels simultaneously, on
the rising edge of CONVST. The aperture time for the track/
holds (i.e., the delay time between the external CONVST signal
and the track/hold actually going into hold) is typically 15␣ns
and, more importantly, is well matched across the four track/
holds on one device and also well matched from device to de-
vice. This allows the relative phase information between differ-
ent input channels to be accurately preserved. It also allows
multiple AD7864s to sample more than four channels simulta-
neously. At the end of a conversion sequence, the part returns
to its tracking mode. The acquisition time of the track/hold
amplifiers begin at this point.
Reference SectionThe AD7864 contains a single reference pin, labelled VREF,
which either provides access to the part’s own +2.5␣V reference
or to which an external +2.5␣V reference can be connected to
provide the reference source for the part. The part is specified
with a +2.5␣V reference voltage. Errors in the reference source
will result in gain errors in the AD7864’s transfer function and
will add to the specified full-scale errors on the part. On the
AD7864-1 and AD7864-3, it will also result in an offset error
injected in the attenuator stage, see Figures 2 and 4.
The AD7864 contains an on-chip +2.5␣V reference. To use this
reference as the reference source for the AD7864, simply con-
nect a 0.1␣mF disc ceramic capacitor from the VREF pin to AGND.
The voltage that appears at this pin is internally buffered before
being applied to the ADC. If this reference is used externally to
the AD7864, it should be buffered, as the part has a FET switch
in series with the reference output resulting in a source imped-
ance for this output of 6␣kW nominal. The tolerance on the
internal reference is –10␣mV at 25°C with a typical temperature
coefficient of 25␣ppm/°C and a maximum error over tempera-
ture of –20␣mV.
If the application requires a reference with a tighter tolerance or
the AD7864 needs to be used with a system reference, the user
has the option of connecting an external reference to this VREF
pin. The external reference will effectively overdrive the internal
reference and thus provide the reference source for the ADC.
The reference input is buffered before being applied to the ADC
with the maximum input current of –100␣mA. Suitable reference
sources for the AD7864 include the AD680, AD780, REF192
and REF43 precision +2.5␣V references.
CIRCUIT DESCRIPTION
Analog Input SectionThe AD7864 is offered as three part types: the AD7864-1,
AD7864-1Figure 2 shows the analog input section of the AD7864-1. Each
input can be configured for –5 V or –10 V operation on the
AD7864-1. For –5 V (AD7864-1) operation, the VINXA and
VINXB inputs are tied together and the input voltage is applied to
both. For –10 V (AD7864-1) operation, the VINXB input is tied
to AGND and the input voltage is applied to the VINXA input.
The VINXA and VINXB inputs are symmetrical and fully inter-
changeable. Thus for ease of PCB layout on the –10 V range,
the input voltage may be applied to the VINXB input while the
VINXA input is tied to AGND.
AGND
VIN1B
VIN1A
VREFFigure 2.AD7864-1 Analog Input Structure
For the AD7864-1, R1 = 6 kW, R2 = 24 kW, R3 = 24 kW and
R4 = 12 kW. The resistor input stage is followed by the high
input impedance stage of the track/hold amplifier.
The designed code transitions take place midway between suc-
cessive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs
etc.) LSB size is given by the formula, 1 LSB = FSR/4096. For
the –5 V range, 1 LSB = 10 V/4096 = 2.44 mV. For the –10 V
range, 1 LSB = 20 V/4096 = 4.88 mV. Output coding is twos
complement binary with 1 LSB = FSR/4096. The ideal input/
output transfer function for the AD7864-1 is shown in Table I.
Table I.Ideal Input/Output Code Table for the AD7864-1NOTESFSR is full-scale range and is 20 V for the –10 V range and 10 V for the –5 V
range, with VREF = +2.5 V.
AD7864-2Figure 3 shows the analog input section of the AD7864-2. Each
input can be configured for 0 V to +5 V operation or 0 V to
+2.5 V operation. For 0 V to +5 V operation, the VINXB input is
tied to AGND and the input voltage is applied to the VINXA
input. For 0 V to 2.5 V operation, the VINXA and VINXB inputs
are tied together and the input voltage is applied to both. The
VINXA and VINXB inputs are symmetrical and fully interchange-
able. Thus for ease of PCB layout on the 0 V to +5 V range, the
input voltage may be applied to the VINXB input while the VINXA
input is tied to AGND.
For the AD7864-2, R1 = 6 kW and R2 = 6 kW. Once again, the
designed code transitions occur on successive integer LSB
values. Output coding is straight (natural) binary with 1 LSB =
FSR/4096 = 2.5 V/4096 = 0.61 mV, and 5 V/4096 = 1.22 mV,
for the 0 V to 2.5 V and the 0 V to 5 V options respectively.
Table II shows the ideal input and output transfer function for
the AD7864-2.
Figure 3.AD7864-2 Analog Input Structure
Table II.Ideal Input/Output Code Table for the AD7864-2NOTESFSR is full-scale range and is 0 V to 2.5 V and 0 V to 5 V for AD7864-2 with
VREF = +2.5 V.1 LSB = FSR/4096 and is 0.61 mV (0 V to 2.5 V) and 1.22 mV (0 V to 5 V) for
AD7864-2 with VREF = +2.5 V.
AD7864
AD7864-3Figure 4 shows the analog input section of the AD7864-3. The
analog input range is –2.5 V on the VIN1A input. The VIN1B
input can be left unconnected but if it is connected to a poten-
tial then that potential must be AGND.
VIN1B
VIN1A
VREFFigure 4.AD7864-3 Analog Input Structure
For the AD7864-3, R1 = 6 kW and R2 = 6 kW. As a result, the
VIN1A input should be driven from a low impedance source. The
resistor input stage is followed by the high input impedance
stage of the track/hold amplifier.
The designed code transitions take place midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs,
etc.) LSB size is given by the formula, 1 LSB = FSR/4096.
Output coding is 2s complement binary with 1 LSB = FSR/
4096 = 5 V/4096 = 1.22 mV. The ideal input/output transfer
function for the AD7864-3 is shown in Table III.
Table III.Ideal Input/Output Code Table for the AD7864-3NOTESFSR is full-scale range is 5 V, with VREF = +2.5 V.1 LSB = FSR/4096 = 1.22 mV (–2.5 V - AD7864-3) with VREF = +2.5 V.
SELECTING A CONVERSION SEQUENCEAny subset of the four channels VIN1 to VIN4 can be selected
for conversion. The selected channels are converted in an
ascending order. For example if the channel selection includes
VIN4, VIN1 and VIN3 then the conversion sequence will be
VIN1, VIN3 and then VIN4. The conversion sequence selection
my be made by using either the hardware channel select input
pins (SL1 through SL4) or programming the channel select
register. A logic high on a hardware channel select pin (or logic
one in the channel select register) when CONVST goes logic
high, marks the associated analog input channel for inclusion in
the conversion sequence.
Figure 5 shows the arrangement used. The H/S SEL controls a
multiplexer which selects the source of the conversion sequence
information, i.e., from the Hardware channel select pins (SL1 to
SL4) or from the channel selection register. When a conversion
is started the output from the multiplexer is latched until the
end of the conversion sequence. The data bus Bits DB0 to DB3
(DB0 representing Channel 1 through DB3 representing Chan-
nel 4) are bidirectional and become inputs to the channel select
register when RD is logic high and CS and WR are logic low.
The logic state on DB0 to DB3 is latched into the channel select
register when WR goes logic high.
Figure 5.Channel Select Inputs and Registers
Figure 6.Channel Selection via Software Control
