AD7863AR-10 ,Simultaneous Sampling Dual 175 kSPS 14-Bit ADCGENERAL DESCRIPTION The AD7863 is fabricated in Analog Devices’ Linear Compat-2The AD7863 is a high ..
AD7863AR-2 ,Simultaneous Sampling Dual 175 kSPS 14-Bit ADCfeatures two complete ADC functions allowingA1and V or V and V ), which can be sampled and converte ..
AD7863AR-3 ,Simultaneous Sampling Dual 175 kSPS 14-Bit ADCSPECIFICATIONS unless otherwise noted.)AB1 1Parameter Version Version Units Test Conditions/Comment ..
AD7863ARS-10 ,Simultaneous Sampling Dual 175 kSPS 14-Bit ADCapplications.and at this time the conversion results for both channels are3. The part offers a high ..
AD7863ARS-2REEL7 , Simultaneous Sampling Dual 175 kSPS 14-Bit ADC
AD7863BR-10 ,Simultaneous Sampling Dual 175 kSPS 14-Bit ADCFEATURES FUNCTIONAL BLOCK DIAGRAMTwo Fast 14-Bit ADCs VV DDREFFour Input Channels2k+2.5VSimultaneo ..
ADM2481BRWZ-RL7 , Half-Duplex, iCoupler Isolated RS-485 Transceiver
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ADM2483BRW ,Slew-Rate Limited Isolated RS-485 Transceiverfeatures protect against The ADM2483 is slew-limited to reduce reflections with output short circui ..
ADM2484EBRWZ-REEL7 , 500 kbps, ESD Protected, Half-/Full-Duplex, iCoupler, Isolated RS-485 Transceiver
ADM2485BRWZ-REEL7 , High Speed, Isolated RS-485 Transceiver with Integrated Transformer Driver
ADM2486BRW ,iCoupler® High Speed Isolated RS-485 TranceiverCharacteristics .... 8 Power Valid Input........ 15 Pin Configuration and Function Descriptions.. 9 ..
AD7863AR-10-AD7863AR-2-AD7863AR-3-AD7863ARS-10-AD7863BR-10
Simultaneous Sampling Dual 175 kSPS 14-Bit ADC
REV.A
Simultaneous Sampling
Dual 175 kSPS 14-Bit ADC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Two Fast 14-Bit ADCs
Four Input Channels
Simultaneous Sampling and Conversion
5.2 �s Conversion Time
Single Supply Operation
Selection of Input Ranges�10 V for AD7863-10
�2.5 V for AD7863-3
0 V to 2.5 V for AD7863-2
High Speed Parallel Interface
Low Power, 70 mW Typ
Power Saving Mode, 105 �W Max
Overvoltage Protection on Analog Inputs
14-Bit Lead Compatible Upgrade to AD7862
APPLICATIONS
AC Motor Control
Uninterrupted Power Supplies
Data Acquisition Systems
Communications
GENERAL DESCRIPTIONThe AD7863 is a high speed, low power, dual 14-bit A/D con-
verter that operates from a single +5V supply. The part contains
two 5.2µs successive approximation ADCs, two track/hold amplifi-
ers, an internal +2.5V reference and a high speed parallel inter-
face. Four analog inputs are grouped into two channels (A and
B) selected by the A0 input. Each channel has two inputs (VA1
and VA2 or VB1 and VB2), which can be sampled and converted
simultaneously thus preserving the relative phase information of
the signals on both analog inputs. The part accepts an analog
input range of ±10V (AD7863-10), ±2.5V (AD7863-3) and
0 V–2.5 V (AD7863-2). Overvoltage protection on the analog
inputs for the part allows the input voltage to go to ±17 V, ±7 V
or +7V respectively, without causing damage.
A single conversion start signal (CONVST) simultaneously
places both track/holds into hold and initiates conversion on
both channels. The BUSY signal indicates the end of conversion
and at this time the conversion results for both channels are
available to be read. The first read after a conversion accesses
the result from VA1 or VB1, while the second read accesses the
result from VA2 or VB2, depending on whether the multiplexer
select A0 is low or high respectively. Data is read from the part
via a 14-bit parallel data bus with standard CS and RD signals.
In addition to the traditional dc accuracy specifications such as
linearity, gain and offset errors, the part is also specified for
dynamic performance parameters including harmonic distortion
and signal-to-noise ratio.
The AD7863 is fabricated in Analog Devices’ Linear Compat-
ible CMOS (LC2MOS) process, a mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. It is available in 28-lead SOIC and SSOP.
PRODUCT HIGHLIGHTS1. The AD7863 features two complete ADC functions allowing
simultaneous sampling and conversion of two channels.
Each ADC has a two-channel input mux. The conversion
result for both channels is available 5.2 µs after initiating
conversion.
2. The AD7863 operates from a single +5V supply and
consumes 70mW typ. The automatic power-down mode,
where the part goes into power down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7863 ideal for battery-powered or portable
applications.
3. The part offers a high speed parallel interface for easy
connection to microprocessors, microcontrollers and digital
signal processors.
4. The part is offered in three versions with different analog
input ranges. The AD7863-10 offers the standard industrial
input range of ±10 V; the AD7863-3 offers the common
signal processing input range of ±2.5 V, while the AD7863-2
can be used in unipolar 0 V–2.5 V applications.
5. The part features very tight aperture delay matching between
the two input sample and hold amplifiers.
AD7863–SPECIFICATIONS
(VDD = +5 V � 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX
unless otherwise noted.)
LOGIC OUTPUTS
CONVERSION RATE
POWER REQUIREMENTS
NOTES
1Temperature ranges are as follows: A, B Versions: –40°C to +85°C.Sample tested during initial release.Applies to Mode 1 operation. See section on operating modes.See Terminology.Sample tested @ +25°C to ensure compliance.This 10 µs includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling
edge of CONVST, for a narrow CONVST pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10 µs. This can be seen from
Figure 6. Note that if the CONVST pulsewidth is greater than 5.2 µs, the effective conversion time will increase beyond 10 µs.Performance measured through full channel (multiplexer, SHA and ADC).For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of
operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore the 40 nA typical figure shown
is a characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The max figure shown in the Conditions/
Comments column reflects the AD7863 with supply decoupling in place—0.1 µF in parallel with a 10 µF disc ceramic capacitors on the VDD pin and 2×0.1 µF disc
ceramic capacitors on the VREF pin, in both cases to the AGND plane.
Specifications subject to change without notice.
AD7863
TIMING CHARACTERISTICS1, 2NOTESSample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6V.See Figure 1.Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8V or 2.0V.These times are derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V � 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX unless
otherwise noted.)Figure 1.Timing Diagram
Figure 2.Load Circuit for Access Time and Bus Relinquish Time
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3V to +7V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3V to +7V
Analog Input Voltage to AGND
AD7863-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±17V
AD7863-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7V
AD7863-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Reference Input Voltage to AGND . . ..–0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . .–0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .110°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .110°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7863 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*R = Small Outline (SOIC), RS = Shrink Small Outline (SSOP).
AD7863
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 14-bit converter, this is 86.04dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7863 it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4 and V5 are the rms amplitudes of the second through the
fifth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb)
and (fa – 2fb).
The AD7863 is tested using two input frequencies. In this case,
the second and third order terms are of different significance.
The second order terms are usually distanced in frequency from
the original sine waves, while the third order terms are usually at
a frequency close to the input frequencies. As a result, the
second and third order terms are specified separately. The
calculation of the intermodulation distortion is as per the THD
specification where it is the ratio of the rms sum of the indi-
vidual distortion products to the rms amplitude of the funda-
mental expressed in dBs.
Channel-to-Channel IsolationChannel-to-Channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 50kHz sine wave signal to all nonselected channels and
determining how much that signal is attenuated in the selected
channel. The figure given is the worst case across all channels.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Positive Gain Error (AD7863-10, �10 V, AD7863-3, �2.5 V)This is the deviation of the last code transition (01...110 to...111) from the ideal 4 × VREF – 1 LSB (AD7863-10
±10 V range) or VREF – 1 LSB (AD7863-3, ±2.5 V range), after
the Bipolar Offset Error has been adjusted out.
Positive Gain Error (AD7863-2, 0 V to 2.5 V)This is the deviation of the last code transition (11...110 to...111) from the ideal VREF – 1 LSB, after the unipolar
offset error has been adjusted out.
Bipolar Zero Error (AD7863-10, �10 V, AD7863-3, �2.5 V)This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal 0 V (AGND).
Unipolar Offset Error (AD7863-2, 0 V to 2.5 V)This is the deviation of the first code transition (00...000 to...001) from the ideal AGND + 1 LSB.
Negative Gain Error (AD7863-10, �10 V, AD7863-3, �2.5 V)This is the deviation of the first code transition (10...000 to...001) from the ideal –4 × VREF + 1 LSB (AD7863-10
±10 V range) or –VREF + 1 LSB (AD7863-3, ±2.5 V range),
after Bipolar Zero Error has been adjusted out.
Track/Hold Acquisition TimeTrack/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected VAX/BX input of the AD7863. It means that the
user must wait for the duration of the track/hold acquisition
time after the end of conversion or after a channel change/step
input change to VAX/BX before starting another conversion, to
ensure that the part operates to specification.
AD7863
CONVERTER DETAILSThe AD7863 is a high speed, low power, dual 14-bit A/D con-
verter that operates from a single +5V supply. The part con-
tains two 5.2µs successive approximation ADCs, two track/
hold amplifiers, an internal +2.5V reference and a high speed
parallel interface. Four analog inputs are grouped into two
channels (A and B) selected by the A0 input. Each channel has
two inputs (VA1 and VA2 or VB1 and VB2) which can be sampled
and converted simultaneously thus preserving the relative phase
information of the signals on both analog inputs. The part
accepts an analog input range of ±10V (AD7863-10), ±2.5V
(AD7863-3) and 0 V–2.5 V (AD7863-2). Overvoltage protec-
tion on the analog inputs for the part allows the input voltage to
go to ±17 V, ±7 V or +7 V respectively, without causing dam-
age. The AD7863 has two operating modes, the high sampling
mode and the auto sleep mode where the part automatically
goes into sleep after the end of conversion. These modes are
discussed in more detail in the Timing and Control section.
Conversion is initiated on the AD7863 by pulsing the CONVST
input. On the falling edge of CONVST, both on-chip track/
holds are simultaneously placed into hold and the conversion
sequence is started on both channels. The conversion clock for
the part is generated internally using a laser-trimmed clock
oscillator circuit. The BUSY signal indicates the end of conver-
sion and at this time the conversion results for both channels
are available to be read. The first read after a conversion ac-
cesses the result from VA1 or VB1, while the second read ac-
cesses the result from VA2 or VB2 depending on whether the
multiplexer select A0 is low or high respectively before the
conversion is initiated. Data is read from the part via a 14-bit
parallel data bus with standard CS and RD signals.
Conversion time for the AD7863 is 5.2µs in the high sampling
mode (10 µs for the auto sleep mode), and the track/hold acqui-
sition time is 0.5µs. To obtain optimum performance from the
part, the read operation should not occur during the conversion
or during the 400 ns prior to the next conversion. This allows
the part to operate at throughput rates up to 175 kHz and
achieve data sheet specifications.
Track/Hold SectionThe track/hold amplifiers on the AD7863 allow the ADCs to
accurately convert an input sine wave of full-scale amplitude to
14-bit accuracy. The input bandwidth of the track/hold is
greater than the Nyquist rate of the ADC, even when the ADC
is operated at its maximum throughput rate of 175kHz (i.e.,
the track/hold can handle input frequencies in excess of 87.5kHz).
The track/hold amplifiers acquire input signals to 14-bit accu-
racy in less than 500ns. The operation of the track/holds are
essentially transparent to the user. The two track/hold amplifi-
ers sample their respective input channels simultaneously, on
the falling edge of CONVST. The aperture time for the track/
holds (i.e., the delay time between the external CONVST signal
and the track/hold actually going into hold) is well matched
across the two track/holds on one device and also well matched
from device to device. This allows the relative phase information
between different input channels to be accurately preserved. It
also allows multiple AD7863s to simultaneously sample more
than two channels. At the end of conversion, the part returns to
its tracking mode. The acquisition time of the track/hold ampli-
fiers begins at this point.
Reference SectionThe AD7863 contains a single reference pin, labeled VREF,
which either provides access to the part’s own +2.5V reference
or to which an external +2.5V reference can be connected to
provide the reference source for the part. The part is specified
with a +2.5V reference voltage. Errors in the reference source
will result in gain errors in the AD7863’s transfer function and
will add to the specified full-scale errors on the part. On the
AD7863-10 and AD7863-3, it will also result in an offset error
injected in the attenuator stage.
The AD7863 contains an on-chip +2.5V reference. To use this
reference as the reference source for the AD7863, simply
connect two 0.1µF disc ceramic capacitors from the VREF pin
to AGND. The voltage that appears at this pin is internally
buffered before being applied to the ADC. If this reference is
required for use external to the AD7863, it should be buffered
as the part has a FET switch in series with the reference output
resulting in a source impedance for this output of 5.5kΩ nomi-
nal. The tolerance on the internal reference is ±10mV at 25°C
with a typical temperature coefficient of 25ppm/°C and a maxi-
mum error over temperature of ±25mV.
If the application requires a reference with a tighter tolerance or
the AD7863 needs to be used with a system reference, the user
has the option of connecting an external reference to this VREF
pin. The external reference will effectively overdrive the internal
reference and thus provide the reference source for the ADC.
The reference input is buffered before being applied to the
ADC with a maximum input current of ±100µA. A suitable
reference source for the AD7863 is the AD780 precision
+2.5V reference.
CIRCUIT DESCRIPTION
Analog Input SectionThe AD7863 is offered as three part types: the AD7863-10,
which handles a ±10 V input voltage range, the AD7863-3,
which handles input voltage range ±2.5 V and the AD7863-2,
which handles a 0V to +2.5V input voltage range.
Figure 3.AD7863-10/-3 Analog Input Structure
Figure 3 shows the analog input section for the AD7863-10 and
AD7863-3. The analog input range of the AD7863-10 is ±10 V
into an input resistance of typically 9 kΩ. The analog input
range of the AD7863-3 is ±2.5 V into an input resistance of
typically 3 kΩ. This input is benign, with no dynamic charging
currents as the resistor stage is followed by a high input imped-
ance stage of the track/hold amplifier. For the AD7863-10, R1
= 8 kΩ, R2 = 2 kΩ and R3 = 2 kΩ. For the AD7863-3, R1 = R2
= 2 kΩ and R3 is open circuit.
For the AD7863-10 and AD7863-3, the designed code transi-
tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs,
3 LSBs . . .). Output coding is twos complement binary with
1 LSB = FS/16384. The ideal input/output transfer function for
the AD7863-10 and AD7863-3 is shown in Table I.
Table I.Ideal Input/Output Code Table for the AD7863-10/-3+FSR/2 – 1 LSB
+FSR/2 – 2 LSBs
+FSR/2 – 3 LSBs
GND + 1 LSB
GND
GND – 1 LSB
NOTESFSR is full-scale range = 20 V (AD7863-10) and = 5 V (AD7863-3) with
REF IN = +2.5 V.1 LSB = FSR/16384 = 1.22 mV (AD7863-10) and 0.3 mV (AD7863-3) with
REF IN = +2.5 V.
The analog input section for the AD7863-2 contains no biasing
resistors and the VAX/BX pin drives the input directly to the
multiplexer and track/hold amplifier circuitry. The analog input
range is 0 V to +2.5 V into a high impedance stage with an
input current of less than 100nA. This input is benign, with no
dynamic charging currents. Once again, the designed code tran-
sitions occur on successive integer LSB values. Output coding is
straight (natural) binary with 1 LSB = FS/16384 = 2.5 V/16384
= 0.15 mV. Table II shows the ideal input/output transfer func-
tion for the AD7863-2.
Table II.Ideal Input/Output Code Table for the AD7863-2NOTESFSR is Full-Scale Range and is 2.5 V for AD7863-2 with VREF = +2.5 V.1 LSB = FSR/16384 and is 0.15 mV for AD7863-2 with VREF = +2.5 V.
OFFSET AND FULL-SCALE ADJUSTMENTIn most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Invariably, some applications will require
that the input signal span the full analog input dynamic range.
In such applications, offset and full-scale error will have to be
adjusted to zero.
Figure 4 shows a typical circuit that can be used to adjust the
offset and full-scale errors on the AD7863 (VA1 on the AD7863-
10 version is shown for example purposes only). Where adjust-
ment is required, offset error must be adjusted before full-scale
error. This is achieved by trimming the offset of the op amp
driving the analog input of the AD7863 while the input voltage is
1/2 LSB below analog ground. The trim procedure is as follows:
apply a voltage of –0.61 mV (–1/2 LSB) at V1 in Figure 4 and
adjust the op amp offset voltage until the ADC output code
flickers between 11 1111 1111 1111 and 00 0000 0000 0000.
