AD7862ARS-10 ,Simultaneous Sampling Dual 250 kSPS 12-Bit ADCfeatures very tight aperture delay matching betweenlinearity, full-scale and offset errors, the par ..
AD7862ARS-2 ,Simultaneous Sampling Dual 250 kSPS 12-Bit ADCfeatures two complete ADC functions allowingchannel has two inputs (V & V or V & V ) that can be si ..
AD7862ARS-3 ,Simultaneous Sampling Dual 250 kSPS 12-Bit ADCSPECIFICATIONS unless otherwise noted.)AB S1Parameter Version Version Version Units Test Conditions ..
AD7862ARSZ-10 ,Simultaneous Sampling Dual 250 kSPS 12-Bit ADCSPECIFICATIONS unless otherwise noted.)AB S1Parameter Version Version Version Units Test Conditions ..
AD7863AR-10 ,Simultaneous Sampling Dual 175 kSPS 14-Bit ADCGENERAL DESCRIPTION The AD7863 is fabricated in Analog Devices’ Linear Compat-2The AD7863 is a high ..
AD7863AR-2 ,Simultaneous Sampling Dual 175 kSPS 14-Bit ADCfeatures two complete ADC functions allowingA1and V or V and V ), which can be sampled and converte ..
ADM242AR ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversHigh Speed, +5 V, 0.1 μFaCMOS RS-232 Drivers/ReceiversADM222/ADM232A/ADM242*FUNCTIONAL BLOCK DIAGRAM
ADM2481BRWZ-RL7 , Half-Duplex, iCoupler Isolated RS-485 Transceiver
ADM2483BRW ,Slew-Rate Limited Isolated RS-485 TransceiverGENERAL DESCRIPTION to form a differential I/O port. When the driver is disabled or The ADM2483 dif ..
ADM2483BRW ,Slew-Rate Limited Isolated RS-485 Transceiverfeatures protect against The ADM2483 is slew-limited to reduce reflections with output short circui ..
ADM2484EBRWZ-REEL7 , 500 kbps, ESD Protected, Half-/Full-Duplex, iCoupler, Isolated RS-485 Transceiver
ADM2485BRWZ-REEL7 , High Speed, Isolated RS-485 Transceiver with Integrated Transformer Driver
AD7862AN-10-AD7862AR-10-AD7862AR-2-AD7862AR-3-AD7862ARS-10-AD7862ARS-2-AD7862ARS-3
Simultaneous Sampling Dual 250 kSPS 12-Bit ADC
REV.0
Simultaneous Sampling
Dual 250 kSPS 12-Bit ADC
FUNCTIONAL BLOCK DIAGRAM
DGND
DB0
BUSY
CONVST
VA1
AGND
VREF
AGND
VDD
DB11
VB1
VA2
VB2
FEATURES
Two Fast 12-Bit ADCs
Four Input Channels
Simultaneous Sampling & Conversionms Throughput Time
Single Supply Operation
Selection of Input Ranges:610 V for AD7862-10
62.5 V for AD7862-3
V to 2.5 V for AD7862-2
High Speed Parallel Interface
Low Power, 60mW typ
Power Saving Mode, 50mW typ
Overvoltage Protection on Analog Inputs
14-Bit Pin Compatible Upgrade (AD7863)
APPLICATIONS
AC Motor Control
Uninterrupted Power Supplies
Data Acquisition Systems
Communications
GENERAL DESCRIPTIONThe AD7862 is a high speed, low power, dual 12-bit A/D
converter that operates from a single +5V supply. The part
contains two 4μs successive approximation ADCs, two track/
hold amplifiers, an internal +2.5V reference and a high speed
parallel interface. There are four analog inputs that are grouped
into two channels (A & B) selected by the A0 input. Each
channel has two inputs (VA1 & VA2 or VB1 & VB2) that can be
sampled and converted simultaneously thus preserving the
relative phase information of the signals on both analog inputs.
The part accepts an analog input range of ±10V (AD7862-10),
±2.5V (AD7862-3) and 0–2.5 V (AD7862-2). Overvoltage
protection on the analog inputs for the part allows the input
voltage to go to ±17 V, ±7 V or +7 V, respectively, without
causing damage.
A single conversion start signal (CONVST) places both track/
holds into hold simultaneously and initiates conversion on both
inputs. The BUSY signal indicates the end of conversion, and
at this time the conversion results for both channels are avail-
able to be read. The first read after a conversion accesses the
result from VA1 or VB1, while the second read accesses the result
from VA2 or VB2, depending on whether the multiplexer select
A0 is low or high, respectively. Data is read from the part via a
12-bit parallel data bus with standard CS and RD signals.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the part is also specified for
dynamic performance parameters including harmonic distortion
and signal-to-noise ratio.
The AD7862 is fabricated in Analog Devices’ Linear Compat-
ible CMOS (LC2MOS) process, a mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. It is available in 28-lead SSOP, SOIC and DIP.
PRODUCT HIGHLIGHTS1. The AD7862 features two complete ADC functions allowing
simultaneous sampling and conversion of two channels. Each
ADC has a 2-channel input mux. The conversion result for
both channels is available 3.6μs after initiating conversion.
2. The AD7862 operates from a single +5V supply and
consumes 60mW typ. The automatic power-down mode,
where the part goes into power down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7862 ideal for battery-powered or portable
applications.
3. The part offers a high speed parallel interface for easy con-
nection to microprocessors, microcontrollers and digital
signal processors.
4. The part is offered in three versions with different analog
input ranges. The AD7862-10 offers the standard industrial
input range of ±10V; the AD7862-3 offers the common
signal processing input range of ±2.5V; while the AD7862-2
can be used in unipolar 0V – +2.5V applications.
5. The part features very tight aperture delay matching between
the two input sample-and-hold amplifiers.
AD7862–SPECIFICATIONS
(VDD = +5 V 6 5%, AGND = DGND = 0 V, REF = Internal. All Specifications TMIN to TMAX
unless otherwise noted.)
AD7862NOTESTemperature ranges are as follows:A, B Versions: –40°C to +85°C;
S Version: –55°C to +125°C.Performance measured through full channel (multiplexer, SHA and ADC).See Terminology.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
Analog Input Voltage to AGND
AD7862-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17V
AD7862-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7V
AD7862-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 670mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 116°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260°C
Ceramic DIP Package, Power Dissipation . . . . . . . . . 670mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 116°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDESample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
AD7862
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
TIMING CHARACTERISTICS1, 2NOTES
1Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6V.
2 See Figure 1.
3Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8V or 2.0V.
4These times are derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V 6 5%, AGND = DGND = 0 V, REF = Internal. All Specifications TMIN to TMAX unless
otherwise noted.)t6
CONVST
BUSY
DATAFigure 1.Timing Diagram
+1.6V
1.6mA
200µA
50pF
OUTPUT
PINFigure 2.Load Circuit for Access Time and Bus Relinquish Time
PIN FUNCTION DESCRIPTION
PIN CONFIGURATION
NC = NO CONNECT
VA1
VB1
AGND
DB11
DB10
DB9
BUSY
VDDDB8
DB7
DGND
CONVST
DB6
DB5VREF
DB4
DB3
DB2
DB1
VA2
DB0
AGND
VB2
AD7862
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7862 it is defined as:
THDdB()=20log
where V1 is the rms amplitude of the fundamental and V2, V3, V4
and V5 are the rms amplitudes of the second through the fifth
harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and
(fa – 2 fb).
The AD7862 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Channel-to-Channel IsolationChannel-to-Channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 100kHz sine wave signal to each of the four inputs
individually. These, in turn, are individually referenced to the
other three channels whose inputs are grounded, and the ADC
output is measured to determine the level of crosstalk from the
other channel. The figure given is the worst case across all four
channels.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the ideal 1LSB
change between any two adjacent codes in the ADC.
Positive Full-Scale ErrorThis is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal 4 × VREF – 3/2 LSB (AD7862-10
±10 V range) or VREF – 3/2 LSB (AD7862-3, ±2.5 V range)
after the Bipolar Offset Error has been adjusted out.
Positive Full-Scale Error (AD7862-2, 0 V to 2.5 V)This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal VREF – 3/2 LSB after the unipolar
offset error has been adjusted out.
Bipolar Zero Error (AD7862-10, 610 V, AD7862-3, 62.5 V)This is the deviation of the midscale transition (all 1s to all 0s)
from the ideal AGND – 1/2 LSB.
Unipolar Offset Error (AD7862-2, 0 V to 2.5 V)This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AGND + 1/2 LSB.
Negative Full-Scale Error (AD7862-1, 610 V; AD7862-3,62.5
V)This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal –4 × VREF + 1/2 LSB (AD7862-10
±10 V range) or –VREF + 1/2 LSB (AD7862-3, ±2.5 V range)
after Bipolar Zero Error has been adjusted out.
Track/Hold Acquisition TimeTrack/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected VAX/BX input of the AD7862. It means that the
user must wait for the duration of the track/hold acquisition
time, after the end of conversion or after a channel change/step
input change to VAX/BX, before starting another conversion to
ensure that the part operates to specification.
CONVERTER DETAILSThe AD7862 is a high speed, low power, dual 12-bit A/D
converter that operates from a single +5V supply. The part
contains two 4μs successive approximation ADCs, two track/
hold amplifiers, an internal +2.5V reference and a high speed
parallel interface. There are four analog inputs that are grouped
into two channels (A & B) selected by the A0 input. Each
channel has two inputs (VA1 & VA2 or VB1 & VB2) that can be
sampled and converted simultaneously thus preserving the
relative phase information of the signals on both analog inputs.
The part accepts an analog input range of±10V (AD7862-10),
±2.5V (AD7862-3) and 0V–2.5 V (AD7862-2). Overvoltage
protection on the analog inputs for the part allows the input
voltage to go to ±17 V, ±7 V or +7 V, respectively, without
causing damage. The AD7862 has two operating modes, the
high sampling mode and the auto sleep mode where the part
automatically goes into sleep after the end of conversion. These
modes are discussed in more detail in the Timing and Control
Section.
Conversion is initiated on the AD7862 by pulsing the CONVST
input. On the falling edge of CONVST, both on-chip track/
holds are placed into hold simultaneously, and the conversion
sequence is started on both channels. The conversion clock for
the part is generated internally using a laser-trimmed clock
oscillator circuit. The BUSY signal indicates the end of
conversion, and at this time the conversion results for both
channels are available to be read. The first read after a conver-
sion accesses the result from VA1 or VB1 while the second read
accesses the result from VA2 or VB2, depending on whether the
multiplexer select A0 is low or high, respectively. Data is read
from the part via a 12-bit parallel data bus with standard CS
and RD signals.
Conversion time for the AD7862 is 3.6μs in the high sampling
mode (6μs for the auto sleep mode), and the track/hold
acquisition time is 0.3μs. To obtain optimum performance
from the part, the read operation should not occur during the
conversion or during 300 ns prior to the next conversion. This
allows the part to operate at throughput rates up to 250 kHz
and achieve data sheet specifications.
Track/Hold SectionThe track/hold amplifiers on the AD7862 allow the ADCs to
accurately convert an input sine wave of full-scale amplitude to
12-bit accuracy. The input bandwidth of the track/hold is
greater than the Nyquist rate of the ADC even when the ADC
is operated at its maximum throughput rate of 250kHz (i.e.,
the track/hold can handle input frequencies in excess of 125kHz).
The track/hold amplifiers acquire input signals to 12-bit
accuracy in less than 400ns. The operation of the track/holds is
essentially transparent to the user. The two track/hold amplifi-
ers sample their respective input channels simultaneously on the
falling edge of CONVST. The aperture time for the track/holds
(i.e., the delay time between the external CONVST signal and
the track/hold actually going into hold) is typically 15ns and,
more importantly, is well matched across the two track/holds on
one device and also well matched from device to device. This
allows the relative phase information between different input
The acquisition time of the track/hold amplifiers begins at
this point.
Reference SectionThe AD7862 contains a single reference pin, labelled VREF,
which either provides access to the part’s own +2.5V reference
or to which an external +2.5V reference can be connected to
provide the reference source for the part. The part is specified
with a +2.5V reference voltage. Errors in the reference source
will result in gain errors in the AD7862’s transfer function and
will add to the specified full-scale errors on the part. On the
AD7862-10 and the AD7862-3, it will also result in an offset
error injected in the attenuator stage.
The AD7862 contains an on-chip +2.5V reference. To use this
reference as the reference source for the AD7862, simply
connect a 0.1μF disc ceramic capacitor from the VREF pin to
AGND. The voltage that appears at this pin is internally
buffered before being applied to the ADC. If this reference is
required for use external to the AD7862, it should be buffered
as the part has a FET switch in series with the reference output,
resulting in a source impedance for this output of 3kΩ nominal.
The tolerance on the internal reference is±10mV at 25°C with
a typical temperature coefficient of 25ppm/°C and a maximum
error over temperature of ±25mV.
If the application requires a reference with a tighter tolerance or
the AD7862 needs to be used with a system reference, the user
has the option of connecting an external reference to this VREF
pin. The external reference will effectively overdrive the internal
reference and provide the reference source for the ADC. The
reference input is buffered before being applied to the ADC
with the maximum input current of ±100μA. Suitable reference
sources for the AD7862 include the AD680, AD780 and
REF43 precision +2.5V references.
CIRCUIT DESCRIPTION
Analog Input SectionThe AD7862 is offered as three part types; the AD7862-10,
which handles a ±10 V input voltage range; the AD7862-3,
which handles input voltage range ±2.5 V; and the AD7862-2,
which handles a 0
AGNDAD7862-10/AD7862-3
VAX
VREFFigure 3.AD7862-10/-3 Analog Input Structure
Figure 3 shows the analog input section for the AD7862-10 and
AD7862-3. The analog input range of the AD7862-10 is ±10 V
AD7862currents, as the resistor stage is followed by a high input
impedance stage of the track/hold amplifier. For the AD7862-10,
R1 = 30 kΩ, R2 = 7.5 kΩ, and R3 = 10 kΩ. For the AD7862-3,
R1 = R2 = 6.5 kΩ and R3 is open circuit.
For the AD7862-10 and AD7862-3, the designed code transi-
tions occur on successive integer LSB values (i.e., 1 LSB,LSBs, 3 LSBs . . .). Output coding is twos complement
binary with 1 LSB = FS/4096. The ideal input/output transfer
function for the AD7862-10 and AD7862-3 is shown in TableI.
Table I.Ideal Input/Output Code Table for the AD7862-10/-3NOTESFSR is full-scale range = 20 V (AD7862-10) and = 5 V (AD7862-3) with
REF IN = +2.5 V.1 LSB = FSR/4096 = 4.883 mV (AD7862-10) and 1.22 mV (AD7862-3) with
REF IN = +2.5 V.
The analog input section for the AD7862-2 contains no biasing
resistors, and the VAX/BX pin drives the input to the multiplexer
and track/hold amplifier circuitry directly. The analog input
range is 0 V to +2.5 V into a high impedance stage with an
input current of less than 500nA. This input is benign with no
dynamic charging currents. Once again, the designed code
transitions occur on successive integer LSB values. Output
coding is straight (natural) binary with 1 LSB = FS/4096 =
2.5V/4096 = 0.61 mV. Table II shows the ideal input/output
transfer function for the AD7862-2.
Table II.Ideal Input/Output Code Table for the AD7862-2NOTESFSR is full-scale range and is 2.5 V for AD7862-2 with VREF = +2.5 V.1 LSB = FSR/4096 and is 0.61 mV for AD7862-2 with VREF = +2.5 V.
OFFSET AND FULL-SCALE ADJUSTMENTIn most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
applications, offset and full-scale error will have to be adjusted
to zero.
Figure 4 shows a circuit that can be used to adjust the offset and
full-scale errors on the AD7862 (VA1 on the AD7862-10 version
is shown for example purposes only). Where adjustment is
required, offset error must be adjusted before full-scale error.
This is achieved by trimming the offset of the op amp driving
the analog input of the AD7862 while the input voltage is a
1/2LSB below analog ground. The trim procedure is as follows:
apply a voltage of –2.44 mV (–1/2 LSB) at VA1 (see Figure 4)
and adjust the op amp offset voltage until the ADC output code
flickers between 1111 1111 1111 and 0000 0000 0000.
Figure 4.Full-Scale Adjust Circuit
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC
positive full scale). The trim procedures for both cases are as
follows:
Positive Full-Scale AdjustApply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at VA1. Adjust
R2 until the ADC output code flickers between 0111 1111 1110
and 0111 1111 1111.
Negative Full-Scale AdjustApply a voltage of –9.9976 V (–FS + 1/2 LSB) at VA1 and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.
An alternative scheme for adjusting full-scale error in systems
that use an external reference is to adjust the voltage at the
VREF pin until the full-scale error for any of the channels is
adjusted out. The good full-scale matching of the channels will
ensure small full-scale errors on the other channels.
TIMING AND CONTROLFigure 5a shows the timing and control sequence required to
obtain optimum performance (Mode 1) from the AD7862. In
the sequence shown, a conversion is initiated on the falling edge
of CONVST. This places both track/holds into hold simulta-
neously, and new data from this conversion is available in the
output register of the AD7862 3.6μs later. The BUSY signal
indicates the end of conversion, and at this time the conversion
results for both inputs are available to be read. A second
