AD7861AP ,11-Bit Resolution Simultaneous Sampling A/D ConverterSPECIFICATIONSParameter AD7861AP Units Conditions/CommentsDC ACCURACYResolution 11 Bits Twos Comple ..
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AD7861AP
11-Bit Resolution Simultaneous Sampling A/D Converter
FUNCTIONAL BLOCK DIAGRAM
REF INBUSY
REF OUT
VIN1
VIN2
VIN3
D11
CLKIN
AUX0
AUX1
AUX2
AUX3
CONVSTRESETM0M1
SGND
AGND
DGND
VDD
AD7861
11-Bit Resolution
Simultaneous Sampling A/D Converter
FEATURES
11-Bit Resolution Analog-to-Digital Converter
Seven Single-Ended Analog Inputs
Four Input Channels Simultaneously Sampled
Expansion with 4 Multiplexed Inputs
Internal 2.5 V Reference
3.2 �s Conversion Time per Channel
User Definable Channel Sequencing
Single Supply +5 V Operation
Double Buffered Register Outputs
6.25 MHz to 12.5 MHz Operating Clock Range
APPLICATIONS
Motor Control
3-Phase Power Measurement
Cellular Phones
Data Acquisition
GENERAL DESCRIPTIONThe AD7861 is a multichannel simultaneous sampling A/D
Converter (ADC) configured for the acquisition of voltage
inputs in a motor control solution or three-phase power system.
The AD7861 combined with Analog Devices’ 16-bit fixed-
point digital signal processor (DSP) provides a low cost 16-bit
fixed-point microcontroller solution.
The input stage has been designed to accommodate the types of
signals frequently found in motor drives. The VIN1, VIN2, and
VIN3 channels are simultaneously sampled inputs suitable for
stator current acquisition. The AUX0–AUX3 channels are
multiplexed and are suitable for slower moving inputs such as
temperature and bus voltage of the diode rectifier output in a
motor control application.
PRODUCT HIGHLIGHTS
Simultaneous Sampling of Four InputsFour channel sample and hold amplifier (SHA) allows out of
phase input signals to be sampled simultaneously, preserving
the relative phase information. Sample-and-hold acquisition
time is 1.6 µs and conversion time per channel is 3.2 µs (using
a 12.5 MHz system clock).
Flexible Analog Channel SequencingAD7861 supports acquisition of 2, 3 or 4 channels per group.
Converted channel results are stored in registers and the data
can be read in any order. The sampling and conversion time
for two channels is 8 µs, three channels is 11.2 µs, and four
channels is 14.4 µs (using a 12.5 MHz system clock).
Single 5 V dc OperationLow power, digital process.
REV. B
AD7861–SPECIFICATIONS
(VDD = 5 V � 5%; TA = –40�C to +85�C; REFIN = 2.5 V; Ext CLK @ 12.5 MHz, unless
otherwise noted)
Table I.AD7861 Timing Parameters (TA = –40�C to +85�C and VDD = +5 V unless otherwise noted)Figure 1. Clock and Reset Timing
CLK
CLK
RESETFigure 2. Write Cycle Timing Diagram
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7861 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Input Voltage . . . . . . . . . . . –0.3 V to VDD
Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Output Swing . . . . . . . . . . . –0.3 V to VDD
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280°CStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD7861
PIN DESCRIPTION
PIN CONFIGURATION
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD7861
RESET
VIN1
VDD
SGND
DGND
DGND
D11
DGNDDGNDM0
CONVST
NC = NO CONNECT
D10
CLK
BUSYS0REFOUTAGND
REFIN
AUX0AUX1
AUX2
AUX3
VIN3
VIN2
ANALOG INPUT BLOCKThe AD7861 is an 11-bit resolution, successive approximation
analog-to-digital (A/D) converter with twos complement output
data format. The analog input range is 0 V–5 V with a 2.5 V
reference as defined by the reference input pin (REFIN). The
AD7861 has an internal 2.5 V ± 5% reference, which is utilized
by connecting the reference output pin (REFOUT) to the
REFIN pin.
The A/D conversion time is determined by the system clock
frequency, which can range from 6.25 MHz to 12.5 MHz.
Forty clock cycles are required to complete each conversion.
There is a 4-channel simultaneous sample and hold amplifier
(SHA) at the AD7861 input stage. This allows up to 4 channels to
be simultaneously held and sequentially digitized. The SHA
acquisition time is 20 clock cycles and is independent of the
number of channels sampled.
The minimum throughput time can be calculated as follows:
where tAA = analog acquisition time, tSHA = SHA acquisition
time, n = # channels, tCONV = conversion time per channel
(40 clock cycles).
A/D conversions are initiated by an external analog sample
clock pin (CONVST).
The CONVST input can be run asynchronous to the AD7861
system clock. When CONVST is run asynchronous from CLK,
the falling edge of CLK subsequent to CONVST high initiates
the conversion.
BUSYThe AD7861 BUSY pin goes low at the start of conversion, and
remains low for 40 clock cycles per channel. When BUSY goes
high, this indicates that the output data buffers have been
updated. Data from the previous conversion can be read up to
(n × 40 – 1) clock cycles after the start of conversion (n =
number of channels converted). Refer to Figure 3.
Figure 3.Busy Pulse Timing
CHANNEL SELECTIONDetermining which channels are converted is dependent on the
settings of M0 and M1. The available channel combinations are:
The user must select which channels to convert using M0/M1, a
minimum of two clock cycles before the start of conversion.
The AD7861 provides 4 auxiliary input channels which can be
individually multiplexed into the auxiliary ADC channel. Pins S0/
S1 are used to multiplex these auxiliary channels according to the
following table. It is important to note that the ADC performs a
series of conversions based on the input voltage on each pin
(including the AUX pin) at the start of the CONVST conversion
pulse. The user must select the auxiliary channel using S0/S1
a minimum of two clock cycles before the start of the conversion
sequence.
DIGITAL INTERFACEThe AD7861 is designed to interface with the ADSP-21xx
family of DSPs. The 12-bit parallel interface can also be used
with other DSPs and microcontrollers.
The 11-bit A/D conversion output occupies the 11 most
significant bits of the 12-bit interface. The LSB (Data Bit 0) is
tied low.
REGISTER BASED INPUT/OUTPUTTo facilitate integration into most designs, a register based
input/output structure is provided. These registers can be
memory mapped into the user’s system along with other
memory mapped peripherals.
REGISTER ADDRESSINGTwo address lines (A0 through A1) are used in conjunction with
control lines (CS, RD) to select registers VIN1, VIN2, VIN3, or
AUX. These control lines are active low. Timing and logical
sense is as for the ADSP-2100 family.
REGISTER LISTINGThe output of each channel is stored in its respective register.
The symbolic names and address locations are listed in the
following table.
AD7861
DESCRIPTION OF THE REGISTERSVIN1, VIN2, VIN3These registers contain the results from
the conversion of the analog input voltages.
AUXIn the AD7861, this register contains the
conversion result of the auxiliary channel
which had been selected by S0, S1.
Reading ResultsThe A/D conversion results for channels VIN1, VIN2, VIN3
and AUX are stored in the VIN1, VIN2, VIN3 and AUX
registers respectively. The twos complement data is left justified
and the LSB (Data Bit 0) is set to zero. The relationship
between input voltage and output coding is shown in Figure 4.
Figure 4.AD7861 Transfer Function
Power Supply Connections and SetupThe nominal power supply level (VDD) is +5V ± 5%. The
positive power supply (VDD) should be connected to Pins 21
and 36. The SGND and DGND pins should be star point
connected to AGND at a point close to the AD7861.
Power supplies should be bypassed at the power pins using a
0.1µF capacitor. A 200nF capacitor should also be connected
between REFIN and SGND.
C2073a
3/00 (rev. B)
PRINTED IN U.S.A.
DIGITAL SIGNAL PROCESSOR INTERFACINGThe AD7861 A/D converter is designed to be easily interfaced
to Analog Devices’ family of Digital Signal Processors (DSPs).
Figure 5 shows the interface between the AD7861 and the
ADSP-2101/2105/2115 16-bit fixed point DSP, and the ADSP-
2171 and ADSP-2181 DSP Microcomputers. FLAGOUT from
the DSP is used to initiate the AD7861 conversion and is also
used in conjunction with the BUSY signal to provide an end of
conversion interrupt for the DSP. With M0 and M1 tied low,
the AD7861 is set up in the VIN2, VIN3 channel conversion
mode. By mapping the 12-bit AD7861 data bus into the top 12
bits of the DSP data bus (D12–D23), full-scale outputs from the
AD7861 can be represented as ±1.0 in fixed point arithmetic.
The AD7861 can operate with a clock frequency in the range of
6.25MHz to 12.5MHz. For the ADSP-2101/2105/2115 the
CLKOUT frequency is the system clock frequency. In the case
of the ADSP-2171/2181, the system clock is internally scaled, aMHz system clock will result in a 20MHz CLKOUT
frequency. If CLKOUT from the ADSP-2171/2181 is above
12.5MHz, then an external clock divide down circuit will be
necessary.
Figure 5.ADI Digital Signal Processor/Microcomputer
Interface
OUTLINE DIMENSIONSDimensions shown in inches and (mm).
44-Lead Plastic Leadless Chip Carrier
(P-44A)
