AD7859ASZ ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit, Parallel Sampling ADCsfeatures a pseudo-AD7859: 1 mW typ @ 10 kSPSdifferential sampling scheme. The AD7859 and AD7859L in ..
AD7859ASZ ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit, Parallel Sampling ADCsSpecifications in () apply to the AD7859L.A MIN MAX1 1Parameter A Version B Version Units Test Cond ..
AD7859BS ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCsSpecifications in () apply to the AD7859L.A MIN MAX1 1Parameter A Version B Version Units Test Cond ..
AD7859LAS ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCsSPECIFICATIONSDD DD IN OUTExternal Reference, f = 4 MHz (for L Version: 1.8 MHz (08C to +708C) and ..
AD7861AP ,11-Bit Resolution Simultaneous Sampling A/D ConverterSPECIFICATIONSParameter AD7861AP Units Conditions/CommentsDC ACCURACYResolution 11 Bits Twos Comple ..
AD7862AN-10 ,Simultaneous Sampling Dual 250 kSPS 12-Bit ADCGENERAL DESCRIPTION The AD7862 is fabricated in Analog Devices’ Linear Compat-2The AD7862 is a high ..
ADM241LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSPECIFICATIONS32L, 34L, 36L, 38L, 39L, 41L);V = +5 V 6 5% (ADM230L, 33L, 35L, 37L); V+ = 7.5 V to 1 ..
ADM241LJRS ,+5 V Powered CMOS RS-232 Drivers/ReceiversSPECIFICATIONS32L, 34L, 36L, 38L, 39L, 41L);V = +5 V 6 5% (ADM230L, 33L, 35L, 37L); V+ = 7.5 V to 1 ..
ADM242AN ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversSpecificationsTwo Drivers and Two Receivers 0.1µFVCCC1+On-Board DC-DC Converters+5V TO +10V0.1µFV+V ..
ADM242AR ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversHigh Speed, +5 V, 0.1 μFaCMOS RS-232 Drivers/ReceiversADM222/ADM232A/ADM242*FUNCTIONAL BLOCK DIAGRAM
ADM2481BRWZ-RL7 , Half-Duplex, iCoupler Isolated RS-485 Transceiver
ADM2483BRW ,Slew-Rate Limited Isolated RS-485 TransceiverGENERAL DESCRIPTION to form a differential I/O port. When the driver is disabled or The ADM2483 dif ..
AD7859ASZ
3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit, Parallel Sampling ADCs
FUNCTIONAL BLOCK DIAGRAM
AIN1
AIN8
REFIN/
REFOUT
CREF1
CREF2
CAL
DVDD
DGND
CLKIN
CONVST
BUSY
SLEEP
AVDDAGND
DB15 – DB0RDCSWRW/BREV.A
3 V to 5 V Single Supply, 200 kSPS
8-Channel, 12-Bit Sampling ADCs
FEATURES
Specified for VDD of 3V to 5.5V
AD7859–200 kSPS; AD7859L–100 kSPS
System and Self-Calibration
Low Power
Normal Operation
AD7859:15mW (VDD = 3 V)
AD7859L:5.5mW (VDD = 3 V)
Using Automatic Power-Down After Conversion (25mW)
AD7859:1.3 mW (VDD = 3 V 10 kSPS)
AD7859L:650 mW (VDD = 3 V 10 kSPS)
Flexible Parallel Interface:
16-Bit Parallel/8-Bit Parallel
44-Pin PQFP and PLCC Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
GENERAL DESCRIPTIONThe AD7859/AD7859L are high speed, low power, 8-channel,
12-bit ADCs which operate from a single 3 V or 5 V power
supply, the AD7859 being optimized for speed and the
AD7859L for low power. The ADC contains self-calibration
and system calibration options to ensure accurate operation over
time and temperature and have a number of power-down
options for low power applications.
The AD7859 is capable of 200 kHz throughput rate while the
AD7859L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7859 and AD7859L input
voltage range is 0 to VREF (unipolar) and –VREF/2 to +VREF/2
about VREF/2 (bipolar) with both straight binary and 2s comple-
ment output coding respectively. Input signal range is to the
supply and the part is capable of converting full-power signals to
100 kHz.
CMOS construction ensures low power dissipation of typically
5.4 mW for normal operation and 3.6 μW in power-down mode.
The part is available in 44-pin, plastic quad flatpack package
(PQFP) and plastic lead chip carrier (PLCC).
*Patent pending.
See page 28 for data sheet index.
PRODUCT HIGHLIGHTSOperation with either 3 V or 5 V power supplies.Flexible power management options including automatic
power-down after conversion.By using the power management options a superior power
performance at slower throughput rates can be achieved.
AD7859:1 mW typ @ 10 kSPS
AD7859L:1 mW typ @ 20 kSPSOperates with reference voltages from 1.2 V to the supply.Analog input ranges from 0 V to VDD.Self and system calibration.Versatile parallel I/O port.Lower power version AD7859L.
DC ACCURACY
AD7859/AD7859L–SPECIFICATIONS1, 2
(AVDD = DVDD = +3.0V to +5.5V, REFIN/REFOUT = 2.5 V
External Reference, fCLKIN = 4 MHz (for L Version: 1.8MHz (08C to +708C) and 1 MHz (–408C to +858C)); fSAMPLE = 200kHz (AD7859) 100kHz
(AD7859L); SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted.) Specifications in () apply to the AD7859L.
NOTESTemperature range as follows:A, B Versions,–40°C to +85°C.Specifications apply after calibration.SNR calculation includes distortion and noise components.Not production tested, guaranteed by characterization at initial product release.All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.
Analog inputs @ AGND.The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7859/AD7859L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × VREF,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF).
This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
AD7859/AD7859L
AD7859/AD7859LNOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.Mark/Space ratio for the master clock input is 40/60 to 60/40.The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-
Down section).Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.t9 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t9, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8MHz master clock.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1 (AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7859 and 1.8 MHz for AD7859L;
TA = TMIN to TMAX, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . 500mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1500 kV
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device.This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied.Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latchup.
TO OUTPUT
PIN
1.6mA IOL
200µA I
+2.1VFigure 1.Load Circuit for Digital Output Timing
Specifications
ORDERING GUIDEEVAL-AD7859CB
NOTES
1Linearity error refers to the integral linearity error.
2P = PLCC; S = PQFP.
3L signifies the low power version.
4This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.
5This board is a complete unit allowing a PC to control and communicate with
all Analog Devices, Inc. evaluation boards ending in the CB designators.
For more information on Analog Devices products and evaluation boards, visit
our World Wide Web home page at http://.
PINOUT FOR PLCC
W/B
REFIN/REFOUT
AVDD
CREF1
AIN0
CREF2
AGND
AIN1
AIN2
AIN3
DVDD
DGND
DB5
DB6
DB7
DB8/HBEN
DB9
DB10
DB11
DB4
CONVSTNCDB14CLKINBUSYDB12DB15DB13WRRDCS
DB1
DB2DB3
AIN4AIN5
AIN6AIN7CAL
SLEEP
DB0
PINOUT FOR PQFP
AD7859/AD7859L
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7859/AD7859L, it is
defined as:
THD(dB)=20log1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Unipolar Offset ErrorThis is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in the unipolar mode.
Positive Full-Scale ErrorThis applies to the unipolar and bipolar modes and is the devia-
tion of the last code transition from the ideal AIN(+) voltage
(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been
adjusted out.
Negative Full-Scale ErrorThis applies to the bipolar mode only and is the deviation of the
first code transition (10 . . . 000 to 10 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – VREF/2 + 0.5 LSB).
Bipolar Zero ErrorThis is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).
Track/Hold Acquisition TimeThe track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental.Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N +1.76)dB
Thus for a 12-bit converter, this is 74dB.
PIN FUNCTION DESCRIPTIONREFOUT
AGND
DVDD
DGND
CREF1
CREF2
AIN1–AIN8
W/B
DB0–DB7
DB8/HBEN
CLKIN
AD7859/AD7859L
AD7859/AD7859L ON-CHIP REGISTERSThe AD7859/AD7859L powers up with a set of default conditions. The only writing that is required is to select the channel configu-
ration. Without performing any other write operations, the AD7859/AD7859L still retains the flexibility for performing a full power-
down and a full self-calibration.
Extra features and flexibility such as performing different power-down options, different types of calibrations, including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7859/AD7859L contains a Control register, ADC output data register, Status register, Test register and 10 Cali-
bration registers. The control register is write-only, the ADC output data register and the status register are read-only, and the testand calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip RegistersWriting
When writing to the AD7859/AD7859L, a 16-bit word of data must be transferred. The 16 bits of data is written as either a 16-bit
word, or as two 8-bit bytes, depending on the logic level at the W/B pin. When W/B is high, the 16 bits are transferred on DB0 to
DB15, where DB0 is the LSB and DB15 is the MSB of the write. When W/B is low, DB8/HBEN assumes its HBEN functionality
and data is transferred in two 8-bit bytes on pins DB0 to DB7, pin DB0 being the LSB of each transfer and pin DB7 being the MSB.
When writing to the AD7859/AD7859L in byte mode, the low byte must be written first followed by the high byte. The two MSBs
of the complete 16-bit word, ADDR1 and ADDR0, are decoded to determine which register is addressed, and the 14 LSBs are writ-
ten to the addressed register. Table I shows the decoding of the address bits, while Figure 2 shows the overall write register hierarchy.
Table I.Write Register AddressingReading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register. As with writing to the AD7859/AD7859L either word or byte mode can be used. When reading
from the calibration registers in byte mode, the low byte must be read first.
Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register un-
til the read selection bits are changed in the control register.
Table II.Read Register Addressing
CONTROL REGISTERThe arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described
below. The power-up status of all bits is 0.
MSB
LSB
CONTROL REGISTER BIT FUNCTION DESCRIPTIONAD7859/AD7859L
Table IV.Calibration Selection
Table IIIa.Channel Selection for AD7859/AD7859L
Differential Sampling (SGL/DIFF = 0)*AIN(+) refers to the positive input seen by the AD7859/AD7859L sample-and-
hold circuitry.
AIN(–) refers to the negative input seen by the AD7859/AD7859L sample-and-
hold circuitry.
Table IIIb.Channel Selection for AD7859/AD7859L
Single-Ended Sampling (SGL/DIFF = 1)
STATUS REGISTERThe arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
STARTFigure 4.Flowchart for Reading the Status Register
MSB
LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
AD7859/AD7859L
CALIBRATION REGISTERSThe AD7859/AD7859L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read
from all 10 calibration registers. In self and system calibration, the part automatically modifies the calibration registers; only if the
user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration RegistersThe calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-
dressed (See Table V). The addressing applies to both the read and write operations for the calibration registers. The user should not
attempt to read from and write to the calibration registers at the same time.
Table V. Calibration Register Addressing
Writing to/Reading from the Calibration RegistersWhen writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
When reading from the calibration registers a write to the con-
trol register is required to set the CALSLT0 and CALSLT1 bits
and also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-
dresses the calibration registers for reading). The calibration
register pointer is reset on writing to the control register setting
the CALSLT1 and CALSLT0 bits, or upon completion of all
the calibration register write/read operations. When reset it
points to the first calibration register in the selected write/read
sequence. The calibration register pointer points to the gain
calibration register upon reset in all but one case, this case being
where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-
bration register is being accessed, the calibration register pointer
is automatically incremented after each full calibration register
write/read operation. The calibration register address pointer is
incremented after the high byte read or write operation in byte
mode. Therefore when reading (in byte mode) from the calibra-
tion registers, the low byte must always be read first, i.e., HBEN
= logic zero. The order in which the 10 calibration registers are
arranged is shown in Figure 5. Read/Write operations may be
aborted at any time before all the calibration registers have been
accessed, and the next control register write operation resets the
calibration register pointer. The flowchart in Figure 6 shows the
sequence for writing to the calibration registers. Figure 7 shows
the sequence for reading from the calibration registers.
CALIBRATION REGISTERS
(1)
(2)
(3)
(10)
CALIBRATION REGISTER ADDRESS POINTER POSITION IS
DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS
ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.When reading from the calibration registers there is always two
leading zeros for each of the registers.
Figure 6.Flowchart for Writing to the Calibration Registers
FINISHED
LAST
REGISTER
WRITE
OPERATION
ABORT
YES
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
READ CAL REGISTER
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11Figure 7. Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration RegisterThe offset calibration register contains 16 bits. The two MSBs
are zero and the 14 LSBs contain offset data. By changing the
contents of the offset register, different amounts of offset on the
analog input signal can be compensated for.Decreasing the
number in the offset calibration register compensates for nega-
tive offset on the analog input signal, and increasing the number
in the offset calibration register compensates for positive offset
on the analog input signal. The default value of the offset cali-
bration register is 0010 0000 0000 0000 approximately. This is
not the exact value, but the value in the offset register should be
close to this value. Each of the 14 data bits in the offset register
is binary weighted; the MSB has a weighting of 5% of the refer-
VREF approximately. The resolution can also be expressed as
±(0.05 × VREF)/213 volts. This equals ±0.015 mV, with a 2.5 V
reference. The maximum offset that can be compensated for is
±5% of the reference voltage, which equates to ±125mV with a
2.5V reference and ±250 mV with a 5 V reference.If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5V, what code needs to be written to the
offset register to compensate for the offset 2.5V reference implies that the resolution in the offset reg-
ister is 5% × 2.5 V/213 = 0.015 mV.+20 mV/0.015mV =
1310.72; rounding to the nearest number gives 1311.In
binary terms this is 00 0101 0001 1111, therefore increase
the offset register by 00 0101 0001 1111.
This method of compensating for offset in the analog input sig-
nal allows for fine tuning the offset compensation. If the offset
on the analog input signal is known, there is no need to apply
the offset voltage to the analog input pins and do a system cali-
bration. The offset compensation can take place in software.
Adjusting the Gain Calibration RegisterThe gain calibration register contains 16 bits. The two MSBs
are zero and the 14 LSBs contain gain data. As in the offset cali-
brating register the data bits in the gain calibration register are
binary weighted, with the MSB having a weighting of 2.5% of
the reference voltage. The gain register value is effectively multi-
plied by the analog input to scale the conversion result over the
full range.Increasing the gain register compensates for a
smaller analog input range and decreasing the gain register com-
pensates for a larger input range. The maximum analog input
range that the gain register can compensate for is 1.025 times
the reference voltage, and the minimum input range is 0.975
times the reference voltage.
AD7859/AD7859Land 1.5 CLKIN periods are allowed for the acquisition time.
With a 1.8 MHz clock, this gives a full cycle time of 10 μs,
which equates to a throughput rate of 100 kSPS.
When using the software conversion start for maximum
throughput, the user must ensure the control register write op-
eration extends beyond the falling edge of BUSY. The falling
edge of BUSY resets the CONVST bit to 0 and allows it to be
reprogrammed to 1 to start the next conversion.
TYPICAL CONNECTION DIAGRAMFigure 8 shows a typical connection diagram for the AD7859/
AD7859L. The AGND and the DGND pins are connected
together at the device for good noise suppression. The first
CONVST applied after power-up starts a self-calibration
sequence. This is explained in the calibration section of this data
sheet. Note that after power is applied to AVDD and DVDD and
the CONVST signal is applied, the part requires (70 ms + 1/
sample rate) for the internal reference to settle and for the self-
calibration on power-up to be completed.
ANALOG
SUPPLY
+3V TO +5V
0.1nF EXTERNAL REF
0.1µF INTERNAL REF
0V TO 2.5V
INPUT
4MHz/1.8MHz
OSCILLATOR
OPTIONAL
EXTERNAL
REFERENCEFigure 8. Typical Circuit
For applications where power consumption is a major concern,
the power-down options can be exercised by writing to the part
and using the SLEEP pin. See the Power-Down section for more
details on low power applications.
CIRCUIT INFORMATIONThe AD7859/AD7859L is a fast, 8-channel, 12-bit, single sup-
ply A/D converter. The part requires an external 4 MHz/1.8
MHz master clock (CLKIN), two CREF capacitors, a CONVST
signal to start conversion and power supply decoupling capaci-
tors. The part provides the user with track/hold, on-chip refer-
ence, calibration features, A/D converter and parallel interface
logic functions on a single chip. The A/D converter section of
the AD7859/AD7859L consists of a conventional successive-ap-
proximation converter based around a capacitor DAC. The
AD7859/AD7859L accepts an analog input range of 0 to +VREF.
VREF can be tied to VDD. The reference input to the part con-
nected via a 150 kΩ resistor to the internal 2.5 V reference and
to the on-chip buffer.
A major advantage of the AD7859/AD7859L is that a conver-
sion can be initiated in software, as well as by applying a signal
to the CONVST pin. The part is available in a 44-pin PLCC or a
44-pin PQFP package, and this offers the user considerable
spacing saving advantages over alternative solutions. The
AD7859L version typically consumes only 5.5mW making it
ideal for battery-powered applications.
CONVERTER DETAILSThe master clock for the part is applied to the CLKIN pin.
Conversion is initiated on the AD7859/AD7859L by pulsing the
CONVST input or by writing to the control register and setting
the CONVST bit to 1. On the rising edge of CONVST (or at
the end of the control register write operation), the on-chip
track/hold goes from track to hold mode. The falling edge of the
CLKIN signal which follows the rising edge of CONVST ini-
tiates the conversion, provided the rising edge of CONVST (or
WR when converting via the control register) occurs typically at
least 10 ns before this CLKIN edge. The conversion takes 16.5
CLKIN periods from this CLKIN falling edge. If the 10 ns set-
up time is not met, the conversion takes 17.5 CLKIN periods.
The time required by the AD7859/AD7859L to acquire a signal
depends upon the source resistance connected to the AIN(+) in-
put. Please refer to the acquisition time section for more details.
When a conversion is completed, the BUSY output goes low,
and the result of the conversion can be read by accessing the
data through the data bus. To obtain optimum performance
from the part, read or write operations should not occur during
the conversion or less than 200ns prior to the next CONVST
rising edge. Reading/writing during conversion typically de-
grades the Signal-to-(Noise + Distortion) by less than 0.5 dBs.
The AD7859 can operate at throughput rates of over 200 kSPS
(up to 100kSPS for the AD7859L).
With the AD7859L, 100kSPS throughput can be obtained as
follows: the CLKIN and CONVST signals are arranged to give
a conversion time of 16.5 CLKIN periods as described above
