AD7858LARS ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCGENERAL DESCRIPTION SERIAL INTERFACE/CONTROL REGISTERThe AD7858/AD7858L are high-speed, low-power, ..
AD7858LARS-REEL ,3 V to 5 V Single Supply, 200 kSPS, 8-Channel, 12-Bit, Serial Sampling ADCSpecifications in ( ) apply to the AD7858L.A MIN MAX1 1Parameter A Version B Version Units Test Con ..
AD7858LBR ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCSpecifications apply after calibration.3SNR calculation includes distortion and noise components.4S ..
AD7859AP ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCsSpecifications in () apply to the AD7859L.A MIN MAX1 1Parameter A Version B Version Units Test Cond ..
AD7859AP ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCsSpecifications apply after calibration.3SNR calculation includes distortion and noise components.4N ..
AD7859AS ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCsGENERAL DESCRIPTIONThe AD7859/AD7859L are high speed, low power, 8-channel,WRDB15 – DB0 RD CS W/B12 ..
ADM239LJN ,+5 V Powered CMOS RS-232 Drivers/ReceiversAPPLICATIONS8 R2R2 9 R2OUT INComputersGNDADM232LPeripherals15ModemsPrinters *INTERNAL 400kW PULL-UP ..
ADM239LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversAPPLICATIONS8 R2R2 9 R2OUT INComputersGNDADM232LPeripherals15ModemsPrinters *INTERNAL 400kW PULL-UP ..
ADM239LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversFEATURESSingle 5 V Power Supply+5V INPUTMeets All EIA-232-E and V.28
ADM239LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*Thermal Impedance, θJA(T = ..
ADM241LAR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*Thermal Impedance, θJA(T = ..
ADM241LARS ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*Thermal Impedance, θJA(T = ..
AD7858AR-AD7858BR-AD7858LARS-AD7858LBR
3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC
FUNCTIONAL BLOCK DIAGRAMREV.B
3 V to 5 V Single Supply, 200kSPS
8-Channel, 12-Bit Sampling ADC
FEATURES
Specified for VDD of 3V to 5.5V
AD7858—200 kSPS; AD7858L—100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
Eight Single-Ended or Four Pseudo-Differential Inputs
Low Power
AD7858: 12 mW (VDD = 3 V)
AD7858L: 4.5 mW (VDD = 3 V)
Automatic Power-Down After Conversion (25�W)
Flexible Serial Interface:
8051/SPI™/QSPI™/�P Compatible
24-Lead DIP, SOIC, and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High-Speed Modems
GENERAL DESCRIPTIONThe AD7858/AD7858L are high-speed, low-power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the
AD7858 being optimized for speed and the AD7858L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system calibration options to en-
sure accurate operation over time and temperature and have a
number of power-down options for low-power applications.
The part powers up with a set of default conditions and can
operate as a read-only ADC.
The AD7858 is capable of 200 kHz throughput rate while the
AD7858L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a
pseudo-differential sampling scheme. The AD7858/AD7858L
voltage range is 0 to VREF with straight binary output coding.
Input signal range is to the supply and the part is capable of con-
verting full power signals to 100 kHz.
CMOS construction ensures low power dissipation of typically
4.5 mW for normal operation and 1.15 mW in power-down
mode with a throughput rate of 10 kSPS (VDD = 3 V). The part
is available in 24-lead, 0.3 inch-wide dual-in-line package
(DIP), 24-lead small outline (SOIC), and 24-lead small shrink
outline (SSOP) packages.
*Patent pending.See page 31 for data sheet index.
SPI and QSPI are trademarks of Motorola, Inc.
PRODUCT HIGHLIGHTSSpecified for 3 V and 5 V supplies.Automatic calibration on power-up.Flexible power management options including automatic
power-down after conversion.Operates with reference voltages from 1.2 V to VDD.Analog input range from 0 V to VDD.Eight single-ended or four pseudo-differential input channels.System and self-calibration.Versatile serial I/O port (SPI/QSPI/8051/µP).Lower power version AD7858L.
AD7858/AD7858L–SPECIFICATIONS1, 2
(AVDD = DVDD = +3.0 V to +5.5 V, REFIN/REFOUT = 2.5 V External
Reference unless otherwise noted, fCLKIN = 4 MHz (1.8 MHz B Grade (0�C to +70�C), 1 MHz A and B Grades (–40�C to +85�C) for L Version); fSAMPLE =
200 kHz (AD7858), 100 kHz (AD7858L); SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted.) Specifications in () apply to the AD7858L.
DYNAMIC PERFORMANCE
NOTESTemperature ranges as follows: A, B Versions: –40°C to +85°C. For L Versions, A and B Versions fCLKIN = 1 MHz over –40°C to +85°C temperature range,
B Version fCLKIN = 1.8 MHz over 0°C to +70°C temperature range.Specifications apply after calibration.SNR calculation includes distortion and noise components.Sample tested @ +25°C to ensure compliance.All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital
outputs. Analog inputs @ AGND.The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7858/AD7858L can calibrate. Note also that these are voltage
spans and are not absolute voltages ( i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±0.05 × VREF, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be
VREF ± 0.025 × VREF). This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
AD7858/AD7858L
AD7858/AD7858LfSCLK
tCONVERT
t13
t14
t15
tCAL1
tCAL2
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
See Table XI and timing diagrams for different interface modes and Calibration.Mark/Space ratio for the master clock input is 40/60 to 60/40.The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1(AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7858 and 1.8/1 MHz for AD7858L;
TA = TMIN to TMAX , unless otherwise noted)
TYPICAL TIMING DIAGRAMSFigures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 100 kHz (AD7858L) or
200 kHz (AD7858), reading and writing must be performed
during conversion as in Figure 3. At least 400 ns acquisition
time must be allowed (the time from the falling edge of BUSY
to the next rising edge of CONVST) before the next conversion
begins to ensure that the part is settled to the 12-bit level. If the
user does not want to provide the CONVST signal, the conver-
sion can be initiated in software by writing to the control register.
Figure 1.Load Circuit for Digital Output Timing
Specifications
Figure 2.AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
Figure 3.AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
AD7858/AD7858L
ORDERING GUIDENOTESLinearity error here refers to integral linearity error.N = Plastic DIP; R = SOIC; RS = SSOP.L signifies the low-power version.This can be used as a stand-alone evaluation board or in conjunction with the EVAL-
CONTROL BOARD for evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with all
Analog Devices evaluation boards ending in the CB designators.
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Analog Input Voltage to AGND . . . .–0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . .–0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . .–0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . .–0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .105°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . .+260°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . .450 mW
θJA Thermal Impedance . . .75°C/W (SOIC) 115°C/W (SSOP)
θJC Thermal Impedance . . . .25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
PIN CONFIGURATIONS
DIP, SOIC, AND SSOP
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7858/AD7858L features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS5AVDD
7CREF1
8CREF2
9–16
AD7858/AD7858L
TERMINOLOGY1
Integral NonlinearityThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Unadjusted ErrorThis is the deviation of the actual code from the ideal code tak-
ing all errors into account (Gain, Offset, Integral Nonlinearity, and
other errors) at any point along the transfer function.
Unipolar Offset ErrorThis is the deviation of the first code transition (00...000 to...001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB).
Positive Full-Scale ErrorThis is the deviation of the last code transition from the ideal
AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset
error has been adjusted out.
Channel-to-Channel IsolationChannel-to-channel isolation is a measure of crosstalk between
the channels. It is measured by applying a full-scale 25 kHz
signal to the other seven channels and determining how much
that signal is attenuated in the channel of interest. The figure
given is the worst case for all channels.
Track/Hold Acquisition TimeThe track/hold amplifier returns into track mode and the end of
conversion. Track/hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N +1.76) dB
Thus for a 12-bit converter, this is 74 dB.AIN(+) refers to the positive input of the pseudo differential pair, and AIN(–)
refers to the negative analog input of the pseudo differential pair or to AGND
depending on the channel configuration.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7858/AD7858L, it is
defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
ON-CHIP REGISTERSThe AD7858/AD7858L powers up with a set of default conditions. The only writing required is to select the channel configuration.
Without performing any other write operations the AD7858/AD7858L still retains the flexibility for performing a full power-down
and a full self-calibration.
Extra features and flexibility, such as performing different power-down options, different types of calibrations including system
calibration, and software conversion start, can be selected by further writing to the part.
The AD7858/AD7858L contains a Control Register, ADC Output Data Register, Status Register, Test Register, and
10 Calibration Registers. The control register is write-only, the ADC output data register and the status register are read-only, andthe test and calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
WritingA write operation to the AD7858/AD7858L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine
which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are
written that the data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the
overall write register hierarchy.
Table I.Write Register Addressing
ReadingTo read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis-
ter until the read selection bits are changed in the Control Register.
Table II.Read Register Addressing
AD7858/AD7858L
CONTROL REGISTERThe arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data.
The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de-
scribed below. The power-up status of all bits is 0.
MSB
LSB
CONTROL REGISTER BIT FUNCTION DESCRIPTION
Table III.Channel Selection*AIN(+) refers to the positive input seen by the AD7858/AD7858L sample and hold circuit,
*AIN(–) refers to the negative input seen by the AD7858/AD7858L sample and hold circuit.
Table IV.Calibration Selection
AD7858/AD7858L
MSB LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
STATUS REGISTERThe arrangement of the Status Register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits
in the status register are described below. The power-up status of all bits is 0.
Figure 6.Flowchart for Reading the Status Register
CALIBRATION REGISTERSThe AD7858/AD7858L has 10 calibration registers in all, eight for the DAC, one for the offset, and one for gain. Data can be written
to or read from all 10 calibration registers. In self- and system calibration the part automatically modifies the calibration registers; only if the
user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration RegistersThe calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-
dressed (see Table V). The addressing applies to both the read and write operations for the calibration registers. The user should not
attempt to read from and write to the calibration registers at the same time.
Table V.Calibration Register Addressing
Writing to/Reading from the Calibration RegistersFor writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
For reading from the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits,
but also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-
dresses the calibration registers for reading). The calibration
register pointer is reset on writing to the control register setting
the CALSLT1 and CALSLT0 bits, or upon completion of all
the calibration register write/read operations. When reset it
points to the first calibration register in the selected write/read
sequence. The calibration register pointer will point to the gain
calibration register upon reset in all but one case, this case being
where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one calibra-
tion register is being accessed the calibration register pointer will
be automatically incremented after each calibration register
write/read operation. The order in which the 10 calibration
registers are arranged is shown in Figure 7. The user may abort
at any time before all the calibration register write/read opera-
tions are completed, and the next control register write opera-
tion will reset the calibration register pointer. The flow chart in
Figure 8 shows the sequence for writing to the calibration regis-
ters and Figure 9 for reading.
Figure 7.Calibration Register Arrangements
When reading from the calibration registers there will always be
two leading zeros for each of the registers. When operating in
Serial Interface Mode 1 the read operations to the calibration
registers cannot be aborted. The full number of read operations
must be completed (see section on Serial Interface Mode 1
Timing for more detail).
Figure 8.Flowchart for Writing to the Calibration Registers
AD7858/AD7858LFigure 9.Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration RegisterThe offset calibration register contains 16 bits, two leading zeros,
and 14 data bits. By changing the contents of the offset register
different amounts of offset on the analog input signal can be
compensated for. Increasing the number in the offset calibration
register compensates for negative offset on the analog input
signal, and decreasing the number in the offset calibration regis-
ter compensates for positive offset on the analog input signal.
The default value of the offset calibration register is 0010 0000
0000 0000 approximately. This is not an exact value, but the
value in the offset register should be close to this value. Each of
the 14 data bits in the offset register is binary weighted; the
MSB has a weighting of 5% of the reference voltage, the MSB-1
has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%,
and so on down to the LSB which has a weighting of 0.0006%.
This gives a resolution of ±0.0006% of VREF approximately.
More accurately the resolution is ±(0.05 × VREF )/213 volts =0.015 mV, with a 2.5 V reference. The maximum offset that
can be compensated for is ±5% of the reference voltage, which
equates to ±125 mV with a 2.5 V reference and ±250 mV with
a 5 V reference.If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5 V what code needs to be written to the
offset register to compensate for the offset2.5 V reference implies that the resolution in the offset regis-
ter is 5% × 2.5 V/213 = 0.015 mV. +20 mV/0.015 mV =
1310.72; rounding to the nearest number gives 1311. In
binary terms this is 0101 0001 1111. Therefore, decrease the
offset register by 0101 0001 1111.
This method of compensating for offset in the analog input
signal allows for fine tuning the offset compensation. If the
offset on the analog input signal is known, there will be no need
to apply the offset voltage to the analog input pins and do a
system calibration. The offset compensation can take place in
software.
Adjusting the Gain Calibration RegisterThe gain calibration register contains 16 bits, two leading 0s
and 14 data bits. The data bits are binary weighted as in the
offset calibration register. The gain register value is effectively
multiplied by the analog input to scale the conversion result
over the full range. Increasing the gain register compensates for
a smaller analog input range and decreasing the gain register
compensates for a larger input range. The maximum analog
input range that the gain register can compensate for is 1.025
times the reference voltage, and the minimum input range is
0.975 times the reference voltage.
CIRCUIT INFORMATIONThe AD7858/AD7858L is a fast, 12-bit single supply A/D con-
verter. The part requires an external 4 MHz/1.8 MHz master
clock (CLKIN), two CREF capacitors, a CONVST signal to start
conversion, and power supply decoupling capacitors. The part
provides the user with track/hold, on-chip reference, calibration
features, A/D converter, and serial interface logic functions on a
single chip. The A/D converter section of the AD7858/AD7858L
consists of a conventional successive-approximation converter
based around a capacitor DAC. The AD7858/AD7858L accepts
an analog input range of 0 to +VDD where the reference can be
tied to VDD. The reference input to the part is buffered on-chip.
A major advantage of the AD7858/AD7858L is that a conversion
can be initiated in software as well as applying a signal to the
CONVST pin. Another innovative feature of the AD7858/
AD7858L is self-calibration on power-up, which is initiated
having a capacitor from the CAL pin to AGND, to give superior
dc accuracy. See Automatic Calibration on Power-Up section.
The part is available in a 24-pin SSOP package and this offers
the user considerable space-saving advantages over alternative
solutions. The AD7858L version typically consumes only
5.5 mW making it ideal for battery-powered applications.
CONVERTER DETAILSThe master clock for the part must be applied to the CLKIN
pin. Conversion is initiated on the AD7858/AD7858L by pulsing
the CONVST input or by writing to the control register and
setting the CONVST bit to 1. On the rising edge of CONVST
(or at the end of the control register write operation), the on-
chip track/hold goes from track to hold mode. The falling edge
of the CLKIN signal that follows the rising edge of the CONVST
signal initiates the conversion, provided the rising edge of
CONVST occurs at least 10 ns typically before this CLKIN
edge. The conversion cycle will take 16.5 CLKIN periods from
this CLKIN falling edge. If the 10 ns setup time is not met, the
conversion will take 17.5 CLKIN periods. The maximum speci-
fied conversion time is 4.6 µs for the AD7858 (18tCLKIN,
CLKIN = 4 MHz) and 10 µs for the AD7858L (18tCLKIN,
CLKIN = 1.8 MHz). When a conversion is completed, the
BUSY output goes low, and then the result of the conversion
can be read by accessing the data through the serial interface.
To obtain optimum performance from the part, the read opera-
tion should not occur during the conversion or 400ns prior to
the next CONVST rising edge. However, the maximum
throughput rates are achieved by reading/writing during conver-
sion, and reading/writing during conversion is likely to degrade
the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7858
can operate at throughput rates up to 200 kHz, 100 kHz for the
AD7858L. For the AD7858 a conversion takes 18 CLKIN
periods; 2 CLKIN periods are needed for the acquisition time
giving a full cycle time of 5 µs (= 200 kHz, CLKIN = 4 MHz).
For the AD7858L 100 kHz throughput can be obtained as
follows: the CLKIN and CONVST signals are arranged to give
a conversion time of 16.5 CLKIN periods as described above,
1.5 CLKIN periods are allowed for the acquisition time. This
gives a full cycle time of 10 µs (=100 kHz, CLKIN = 1.8 MHz).
When using the software conversion start for maximum through-
put the user must ensure the control register write operation
extends beyond the falling edge of BUSY. The falling edge of
BUSY resets the CONVST bit to 0 and allows it to be repro-
grammed to 1 to start the next conversion.
TYPICAL CONNECTION DIAGRAMFigure 10 shows a typical connection diagram for the AD7858/
AD7858L. The AGND and the DGND pins are connected
together at the device for good noise suppression. The CAL pin
has a 0.01 µF capacitor to enable an automatic self-calibration
on power-up. The conversion result is output in a 16-bit word
with four leading zeros followed by the MSB of the 12-bit result.
Note that after the AVDD and DVDD power-up the part will
AD7858/AD7858Lrequire approximately 150 ms for the internal reference to settle
and for the automatic calibration on power-up to be completed.
For applications where power consumption is a major concern
then the SLEEP pin can be connected to DGND. See Power-
Down section for more detail on low power applications.
ANALOG INPUTThe equivalent circuit of the analog input section is shown in
Figure 11. During the acquisition interval the switches are both
in the track position and the AIN(+) charges the 20 pF capacitor
through the 125 Ω resistance. On the rising edge of CONVST
switches SW1 and SW2 go into the hold position retaining
charge on the 20 pF capacitor as a sample of the signal on
AIN(+). The AIN(–) is connected to the 20 pF capacitor, and
this unbalances the voltage at node A at the input of the com-
parator. The capacitor DAC adjusts during the remainder of the
conversion cycle to restore the voltage at node A to the correct
value. This action transfers a charge, representing the analog
input signal, to the capacitor DAC which in turn forms a digital
representation of the analog input signal. The voltage on the
AIN(–) pin directly influences the charge transferred to the
capacitor DAC at the hold instant. If this voltage changes dur-
ing the conversion period, the DAC representation of the analog
input voltage will be altered. Therefore it is most important that
the voltage on the AIN(–) pin remains constant during the conver-
sion period. Furthermore it is recommended that the AIN(–)
pin is always connected to AGND or to a fixed dc voltage.
Acquisition TimeThe track and hold amplifier enters its tracking mode on the
falling edge of the BUSY signal. The time required for the track
and hold amplifier to acquire an input signal will depend on
how quickly the 20 pF input capacitance is charged. The acqui-
sition time is calculated using the formula:
where RIN is the source impedance of the input signal, and
125 Ω, 20 pF is the input R, C.
Figure 11.Analog Input Equivalent Circuit
DC/AC ApplicationsFor dc applications high source impedances are acceptable
provided there is enough acquisition time between conversions
to charge the 20 pF capacitor. The acquisition time can be
calculated from the above formula for different source imped-
ances. For example with RIN = 5 kΩ, the required acquisition
time will be 922 ns.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the AIN(+) pin as shown in Figure 13. In applica-
tions where harmonic distortion and signal to noise ratio are
critical the analog input should be driven from a low impedance
source. Large source impedances will significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp will be a func-
tion of the particular application.
When no amplifier is used to drive the analog input the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will de-
grade. Figure 12 shows a graph of the total harmonic distortion
versus analog input signal frequency for different source imped-
ances. With the setup as in Figure 13, the THD is at the –90dB
level. With a source impedance of 1kΩ and no capacitor on the
AIN(+) pin, the THD increases with frequency.
Figure 12.THD vs. Analog Input Frequency
In a single supply application (both 3 V and 5 V), the V+ and
V– of the op amp can be taken directly from the supplies to the
AD7858/AD7858L which eliminates the need for extra external
power supplies. When operating with rail-to-rail inputs and
outputs, at frequencies greater than 10 kHz care must be taken
in selecting the particular op amp for the application. In particu-
lar for single supply applications the input amplifiers should be
connected in a gain of –1 arrangement to get the optimum per-
formance. Figure 13 shows the arrangement for a single supply
application with a 50 Ω and 10 nF low-pass filter (cutoff fre-
quency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a
capacitor with good linearity to ensure good ac performance.
Recommended single supply op amps are the AD820 and the
AD820-3 V.
