AD7856AN ,5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADCSpecifications.1 1Parameter A Version K Version Units Test Conditions/CommentsDYNAMIC PERFORMANCE f ..
AD7858AR ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCSpecifications in ( ) apply to the AD7858L.A MIN MAX1 1Parameter A Version B Version Units Test Con ..
AD7858BR ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCFEATURESSpecified for V of 3 V to 5.5 VDDAD7858—200 kSPS; AD7858L—100 kSPSAVDD AGNDSystem and Self- ..
AD7858LARS ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCGENERAL DESCRIPTION SERIAL INTERFACE/CONTROL REGISTERThe AD7858/AD7858L are high-speed, low-power, ..
AD7858LARS-REEL ,3 V to 5 V Single Supply, 200 kSPS, 8-Channel, 12-Bit, Serial Sampling ADCSpecifications in ( ) apply to the AD7858L.A MIN MAX1 1Parameter A Version B Version Units Test Con ..
AD7858LBR ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCSpecifications apply after calibration.3SNR calculation includes distortion and noise components.4S ..
ADM239LAN ,+5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION All members of the ADM230L family, except the ADM231LThe ADM2xx family of line ..
ADM239LAR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications120 kB/s Data Rate1 16C1+ +5V TO +10V VCCOn-Board DC-DC Converters 1m F 1m F 1m FVOLT ..
ADM239LJN ,+5 V Powered CMOS RS-232 Drivers/ReceiversAPPLICATIONS8 R2R2 9 R2OUT INComputersGNDADM232LPeripherals15ModemsPrinters *INTERNAL 400kW PULL-UP ..
ADM239LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversAPPLICATIONS8 R2R2 9 R2OUT INComputersGNDADM232LPeripherals15ModemsPrinters *INTERNAL 400kW PULL-UP ..
ADM239LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversFEATURESSingle 5 V Power Supply+5V INPUTMeets All EIA-232-E and V.28
ADM239LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*Thermal Impedance, θJA(T = ..
AD7856AN
5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC
REV.A
5 V Single Supply, 8-Channel
14-Bit 285 kSPS Sampling ADC
FUNCTIONAL BLOCK DIAGRAM
AVDDAGND
DVDD
DGND
CLKIN
CONVST
BUSY
SLEEP
CAL
CREF2
CREF1
REFIN/REFOUT
AIN8
AIN1
DINDOUTSCLKSYNC
PRODUCT HIGHLIGHTSSingle 5 V supply.Automatic calibration on power-up.Flexible power management options including automatic
power-down after conversion.Operates with reference voltages from 1.2 V to VDD.Analog input range from 0 V to VDD.Eight single-ended or four pseudo-differential input channels.Self- and system calibration.Versatile serial I/O port (SPI/QSPI/8051/mP).
GENERAL DESCRIPTIONThe AD7856 is a high speed, low power, 14-bit ADC that oper-
ates from a single 5 V power supply. The ADC powers up with
a set of default conditions at which time it can be operated as a
read only ADC. The ADC contains self-calibration and system
calibration options to ensure accurate operation over time and
temperature and it has a number of power-down options for low
power applications.
The AD7856 is capable of 285 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7856 voltage range is 0 to
VREF with straight binary output coding. Input signal range is to
the supply and the part is capable of converting full power sig-
nals to 10 MHz.
CMOS construction ensures low power dissipation of typically
60 mW for normal operation and 5.1 mW in power-down mode
at 10 kSPS throughput rate. The part is available in 24-lead,
0.3 inch-wide dual in-line package (DIP), 24-lead small outline
(SOIC) and 24-lead small shrink outline (SSOP) packages.
Please see page 31 for data sheet index.
FEATURES
Single 5␣V Supply
285 kSPS Throughput Rate
Self- and System Calibration with Autocalibration on
Power-Up
Eight Single-Ended or Four Pseudo-Differential Inputs
Low Power: 60 mW Typ
Automatic Power-Down After Conversion (2.5␣mW Typ)
Flexible Serial Interface: 8051/SPI™/QSPI™/mP Compatible
24-Lead DIP, SOIC and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed ModemsSPI and QSPI are trademarks of Motorola, Inc.
AD7856–SPECIFICATIONS1, 2
A Grade: fCLKIN = 6 MHz, (–408C to +1058C), fSAMPLE = 285 kHz; K Grade:
fCLKIN = 4 MHz, (08C to +1058C), fSAMPLE = 102 kHz; (AVDD = DVDD = +5.0 V 6 5%,
REFIN/REFOUT = 4.096 V External Reference unless otherwise noted, SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted.) Specifica-
tions apply for Mode 2 operation, standard 3-wire SPI interface; refer to Detailed Timing section for Mode 1 Specifications.
AD7856POWER PERFORMANCE
NOTESTemperature ranges as follows: A Version: –40°C to +105°C. K Version: 0°C to +105°C.Specifications apply after calibration.SNR calculation includes distortion and noise components.Sample tested @ +25°C to ensure compliance.All digital inputs @ DGND except for CONVST, SLEEP, CAL and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.
Analog inputs @ AGND.The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7856 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) –0.0375 · VREF, and
the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF – 0.01875 · VREF).
This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
AD7856
TIMING SPECIFICATIONS1(VDD = 5 V; TA = TMIN to TMAX, unless otherwise noted. A Grade: fCLKIN = 6 MHz; K Grade: fCLKIN = 4 MHz.)fSCLK
t13
t14
t15
tCAL2
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
See Table X and timing diagrams for different interface modes and calibration.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t14, quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
Specifications subject to change without notice.
TYPICAL TIMING DIAGRAMSFigures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 285 kHz, reading and writ-
ing must be performed during conversion as in Figure 3. At
least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the CONVST signal, the conversion can be initiated in software
by writing to the control register.
Figure 2.Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
Figure 3.Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
TO OUTPUT
PIN
100pF
+2.1VFigure 1.Load Circuit for Digital Output Timing
Specifications
AD7856
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7856 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .␣–0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . .␣–0.3 V to +7 V
AVDD to DVDD␣ . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Analog Input Voltage to AGND . . . .␣–0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . .–0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . .–0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . .␣–0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2␣ . . . . . . .–10 mA
Operating Temperature Range Commercial
A Version . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +105°C
K Version . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +105°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .105°C/WJC Thermal Impedance . . . . . . . . . . . . . . . . . . . .34.7°C/W
Lead Temperature, (Soldering, 10 secs) . . . . . . . . .+260°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . .450 mWJA Thermal Impedance .75°C/W (SOIC) 115°C/W (SSOP)JC Thermal Impedance . .25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1 kV
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
PIN CONFIGURATIONS
(DIP, SOIC AND SSOP)
ORDERING GUIDENOTESLinearity error here refers to integral linearity error.N = Plastic DIP; R = SOIC; RS = SSOP.This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with
all Analog Devices evaluation boards ending in the CB designators.
PIN FUNCTION DESCRIPTIONS
AD7856
TERMINOLOGY1
Integral NonlinearityThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Unadjusted ErrorThis is the deviation of the actual code from the ideal code
taking all errors into account (Gain, Offset, Integral Nonlinearity
and other errors) at any point along the transfer function.
Unipolar Offset ErrorThis is the deviation of the first code transition (00␣.␣.␣.␣000 to
00␣.␣.␣.␣001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB).
Positive Full-Scale ErrorThis is the deviation of the last code transition from the ideal
AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset
error has been adjusted out.
Channel-to-Channel IsolationChannel-to-channel isolation is a measure of crosstalk between
the channels. It is measured by applying a full-scale 25 kHz
signal to the other seven channels and determining how much
that signal is attenuated in the channel of interest. The figure
given is the worst case for all channels.
Track/Hold Acquisition TimeThe track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within –1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 14-bit converter, this is 86 dB.
NOTEAIN(+) refers to the positive input of the pseudo-differential pair, and AIN(–)
refers to the negative analog input of the pseudo-differential pair or to AGND
depending on the channel configuration.
Total Harmonic DistortionTotal Harmonic Distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7856, it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
Full Power BandwidthThe Full Power Bandwidth (FPBW) of the AD7856 is that
frequency at which the amplitude of the reconstructed (using
FFTs) fundamental (neglecting harmonics and SNR) is reduced
by 3 dB for a full-scale input.
ON-CHIP REGISTERSThe AD7856 powers up with a set of default conditions. The only writing that is required is to select the channel configuration.
Without performing any other write operations the AD7856 still retains the flexibility for performing a full power-down, and a full
self-calibration.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by further writing to the part.
The AD7856 contains a Control Register, ADC Output Data Register, Status Register, Test Register and ten Calibration
Registers. The control register is write only, the ADC output data register and the status register are read only, and the test andcalibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
WritingA write operation to the AD7856 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register
is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the
data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the overall write
register hierarchy.
Table I.Write Register Addressing
ReadingTo read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis-
ter until the read selection bits are changed in the Control Register.
Table II.Read Register Addressing
AD7856
CONTROL REGISTERThe arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data.
The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de-
scribed below. The power-up status of all bits is 0.
LSB
CONTROL REGISTER BIT FUNCTION DESCRIPTION
Table III.Channel Selection*AIN(+) refers to the positive input seen by the AD7856 sample and hold circuit.
AIN(–) refers to the negative input seen by the AD7856 sample and hold circuit.
Table IV.Calibration Selection
AD7856
STATUS REGISTERThe arrangement of the Status Register is shown below. The status register is a read only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
Figure 6.Flowchart for Reading the Status Register
LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
CALIBRATION REGISTERSThe AD7856 has ten calibration registers in all, eight for the
DAC, one for the offset and one for gain. Data can be written
to or read from all ten calibration registers. In self- and system
calibration the part automatically modifies the calibration regis-
ters; only if the user needs to modify the calibration registers
should an attempt be made to read from and write to the cali-
bration registers.
Addressing the Calibration RegistersThe calibration selection bits in the control register CALSLT1
and CALSLT0 determine which of the calibration registers are
addressed (see Table V). The addressing applies to both the
read and write operations for the calibration registers. The user
should not attempt to read from and write to the calibration
registers at the same time.
Table V.Calibration Register Addressing
Writing to/Reading from the Calibration RegistersFor writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
For reading from the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits,
but also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-
dresses the calibration registers for reading). The calibration
register pointer is reset upon writing to the control register
setting the CALSLT1 and CALSLT0 bits, or upon completion
of all the calibration register write/read operations. When reset,
it points to the first calibration register in the selected write/
read sequence. The calibration register pointer will point to the
gain calibration register upon reset in all but one case, this case
being where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-
bration register is being accessed the calibration register pointer
will be automatically incremented after each calibration register
write/read operation. The order in which the ten calibration
registers are arranged is shown in Figure 7. The user may abort
at any time before all the calibration register write/read opera-
tions are completed, and the next control register write opera-
tion will reset the calibration register pointer. The flowchart in
Figure 8 shows the sequence for writing to the calibration regis-
ters and Figure 9 for reading.
Figure 7.Calibration Register Arrangements
When reading from the calibration registers there will always be
two leading zeros for each of the registers. When operating in
Serial Interface Mode 1 the read operations to the calibration
registers cannot be aborted. The full number of read operations
must be completed (see section on Serial Interface Mode 1
Timing for more detail).
Figure 8.Flowchart for Writing to the Calibration
Registers
AD7856Figure 9.Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration RegisterThe offset calibration register contains 16 bits, two leading zeros
and 14 data bits. By changing the contents of the offset register
different amounts of offset on the analog input signal can be
compensated for. Increasing the number in the offset calibration
register compensates for negative offset on the analog input
signal, and decreasing the number in the offset calibration regis-
ter compensates for positive offset on the analog input signal.
The default value of the offset calibration register is approxi-
mately 0010 0000 0000 0000. This is not an exact value, but
the value in the offset register should be close to this value. Each
of the 14 data bits in the offset register is binary weighted: the
MSB has a weighting of 5% of the reference voltage, the MSB-1
has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%,
and so on down to the LSB, which has a weighting of 0.0006%.
This gives a resolution of approximately –0.0006% of VREF.
More accurately the resolution is –(0.05 · VREF )/213 volts =0.015 mV, with a 2.5 V reference. The maximum specified
offset that can be compensated for is –3.75% of the reference
voltage but is typically –5%, which equates to –125 mV with a
2.5 V reference and –250 mV with a 5 V reference.If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5 V, what code needs to be written to the
offset register to compensate for the offset2.5 V reference implies that the resolution in the offset regis-
ter is 5% · 2.5 V/213 = 0.015 mV. +20 mV/0.015 mV =
1310.72; rounding to the nearest number gives 1311. In
binary terms this is 0101 0001 1111. Therefore, decrease the
offset register by 0101 0001 1111.
This method of compensating for offset in the analog input
signal allows for fine tuning the offset compensation. If the
offset on the analog input signal is known, there will be no need
to apply the offset voltage to the analog input pins and do a
system calibration. The offset compensation can take place in
software.
Adjusting the Gain Calibration RegisterThe gain calibration register contains 16 bits, two leading 0s
and 14 data bits. The data bits are binary weighted as in the
offset calibration register. The gain register value is effectively
multiplied by the analog input to scale the conversion result
over the full range. Increasing the gain register compensates for
a smaller analog input range and decreasing the gain register
compensates for a larger input range. The maximum analog
input range for which the gain register can compensate is
1.01875 times the reference voltage; the minimum input range
is 0.98125 times the reference voltage.
CIRCUIT INFORMATIONThe AD7856 is a fast, 14-bit single supply A/D converter. The
part requires an external 6 MHz/4 MHz master clock (CLKIN),
two CREF capacitors, a CONVST signal to start conversion and
power supply decoupling capacitors. The part provides the user
with track/hold, on-chip reference, calibration features, A/D
converter and serial interface logic functions on a single chip.
The A/D converter section of the AD7856 consists of a conven-
tional successive-approximation converter based around a ca-
pacitor DAC. The AD7856 accepts an analog input range of 0
to +VDD where the reference can be tied to VDD. The reference
input to the part is buffered on-chip.
A major advantage of the AD7856 is that a conversion can be
initiated in software as well as applying a signal to the CONVST
pin. Another innovative feature of the AD7856 is self-calibration
on power-up, which is initiated having a 0.01 mF capacitor from
the CAL pin to DGND, to give superior dc accuracy. The part
should be allowed 150 ms after power up to perform this auto-
matic calibration before any reading or writing takes place. The
part is available in a 24-pin SSOP package and this offers the
user considerable spacing saving advantages over alternative
solutions.
CONVERTER DETAILSThe master clock for the part must be applied to the CLKIN
pin. Conversion is initiated on the AD7856 by pulsing the
CONVST input or by writing to the control register and setting
the CONVST bit to 1. On the rising edge of CONVST (or at
the end of the control register write operation), the on-chip
track/hold goes from track to hold mode. The falling edge of the
CLKIN signal that follows the rising edge of the CONVST
signal initiates the conversion, provided the rising edge of
CONVST occurs at least 10 ns typically before this CLKIN
edge. The conversion cycle will take 20 CLKIN periods from
this CLKIN falling edge. If the 10 ns setup time is not met, the
conversion will take 21 CLKIN periods. The maximum speci-
fied conversion time is 3.5 ms (6 MHz) 5.25 ms (4 MHz) for the
AD7856. When a conversion is completed, the BUSY output
goes low, and then the result of the conversion can be read by
accessing the data through the serial interface. To obtain opti-
mum performance from the part, the read operation should not
occur during the conversion or 500␣ns prior to the next CONVST
rising edge. However, the maximum throughput rates are achieved
by reading/writing during conversion, and reading/writing during
conversion is likely to degrade the Signal to (Noise + Distor-
tion) by only 0.5 dBs. The AD7856 can operate at throughput
rates up to 285 kHz. For the AD7856 a conversion takes 21
CLKIN periods; two CLKIN periods are needed for the acqui-
sition time, giving a full cycle time of 3.66 ms (= 260 kHz, CLKIN
= 6 MHz). When using the software conversion start for maximum
throughput the user must ensure the control register write op-
eration extends beyond the falling edge of BUSY. The falling
edge of BUSY resets the CONVST bit to 0 and allows it to be
reprogrammed to 1 to start the next conversion.
TYPICAL CONNECTION DIAGRAMFigure 10 shows a typical connection diagram for the AD7856.
The AGND and DGND pins are connected together at the
device for good noise suppression. The CAL pin has a 0.01 mF
capacitor to enable an automatic self-calibration on power-up.
The conversion result is output in a 16-bit word with two lead-
ing zeros followed by the MSB of the 14-bit result. Note that
after the AVDD and DVDD power-up the part will require 150 ms
for the internal reference to settle and for the automatic calibra-
tion on power-up to be completed.
For applications where power consumption is a major concern
the SLEEP pin can be connected to DGND. See Power-Down
section for more detail on low power applications.
AD7856
ANALOG INPUTThe equivalent circuit of the analog input section is shown in
Figure 11. During the acquisition interval the switches are both
in the track position and the AIN(+) charges the 20 pF capaci-
tor through the 125 W resistance. On the rising edge of CONVST
switches SW1 and SW2 go into the hold position retaining
charge on the 20 pF capacitor as a sample of the signal on
AIN(+). The AIN(–) is connected to the 20 pF capacitor, and
this unbalances the voltage at node A at the input of the com-
parator. The capacitor DAC adjusts during the remainder of the
conversion cycle to restore the voltage at node A to the correct
value. This action transfers a charge, representing the analog
input signal, to the capacitor DAC which in turn forms a digital
representation of the analog input signal. The voltage on the
AIN(–) pin directly influences the charge transferred to the
capacitor DAC at the hold instant. If this voltage changes dur-
ing the conversion period, the DAC representation of the analog
input voltage will be altered. Therefore it is most important that
the voltage on the AIN(–) pin remains constant during the con-
version period. Furthermore, it is recommended that the AIN(–)
pin is always connected to AGND or to a fixed dc voltage.
COMPARATOR
NODE ASW1
TRACK
HOLD
125VAIN(+)
AIN(–)
CREF2
125VFigure 11.Analog Input Equivalent Circuit
Acquisition TimeThe track and hold amplifier enters its tracking mode on the
falling edge of the BUSY signal. The time required for the track
and hold amplifier to acquire an input signal will depend on
how quickly the 20 pF input capacitance is charged. The acqui-
sition time is calculated using the formula:
tACQ = 10 · (RIN + 125 W) · 20 pF
where RIN is the source impedance of the input signal, and
125 W, 20 pF is the input RC.
DC/AC ApplicationsFor dc applications high source impedances are acceptable
provided there is enough acquisition time between conversions
to charge the 20 pF capacitor. The acquisition time can be
calculated from the above formula for different source imped-
ances. For example, with RIN = 5 kW the required acquisition
time will be 1025 ns.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the AIN(+) pin as shown in Figure 13. In applica-
tions where harmonic distortion and signal-to-noise ratio are
critical, the analog input should be driven from a low impedance
source. Large source impedances will significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp will be a func-
tion of the particular application.
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will de-
grade. Figure 12 shows a graph of the total harmonic distortion
versus analog input signal frequency for different source imped-
ances. With the setup as in Figure 13, the THD is at the –90␣dB
level. With a source impedance of 1␣kW and no capacitor on the
AIN(+) pin, the THD increases with frequency.
THD – dB
INPUT FREQUENCY – kHz
140120100Figure 12.THD vs. Analog Input Frequency
In a single supply application (5 V), the V+ and V– of the op
amp can be taken directly from the supplies to the AD7856
which eliminates the need for extra external power supplies.
When operating with rail-to-rail inputs and outputs, at frequen-
cies greater than 10 kHz care must be taken in selecting the
particular op amp for the application. In particular for single
supply applications the input amplifiers should be connected in
a gain of –1 arrangement to get the optimum performance.
Figure 13 shows the arrangement for a single supply application
with a 50 W and 10 nF low-pass filter (cutoff frequency 320 kHz)
on the AIN(+) pin. Note that the 10 nF is a capacitor with good
linearity to ensure good ac performance. Recommended single
supply op amp is the AD820.
AD820
0.1mF
TO AIN(+)
AD7856
VIN
(0 TO VREF)
VREF
+5VFigure 13.Analog Input Buffering
Input RangeThe analog input range for the AD7856 is 0 V to VREF. The
AIN(–) pin on the AD7856 can be biased up above AGND, if
required. The advantage of biasing the lower end of the analog
input range away from AGND is that the user does not need to
have the analog input swing all the way down to AGND. This
has the advantage in true single supply applications that the
input amplifier does not need to swing all the way down to
AGND. The upper end of the analog input range is shifted up
by the same amount. Care must be taken so that the bias ap-
