AD7854LAR ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsSpecifications apply after calibration.3Not production tested. Guaranteed by characterization at in ..
AD7854LARS ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD7854/AD7854L is a high speed, low power, 12-bit ADC 1. ..
AD7856AN ,5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADCSpecifications.1 1Parameter A Version K Version Units Test Conditions/CommentsDYNAMIC PERFORMANCE f ..
AD7858AR ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCSpecifications in ( ) apply to the AD7858L.A MIN MAX1 1Parameter A Version B Version Units Test Con ..
AD7858BR ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCFEATURESSpecified for V of 3 V to 5.5 VDDAD7858—200 kSPS; AD7858L—100 kSPSAVDD AGNDSystem and Self- ..
AD7858LARS ,3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCGENERAL DESCRIPTION SERIAL INTERFACE/CONTROL REGISTERThe AD7858/AD7858L are high-speed, low-power, ..
ADM238LJR-REEL , 5 V-Powered CMOS RS-232 Drivers/Receivers
ADM239LAN ,+5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION All members of the ADM230L family, except the ADM231LThe ADM2xx family of line ..
ADM239LAR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications120 kB/s Data Rate1 16C1+ +5V TO +10V VCCOn-Board DC-DC Converters 1m F 1m F 1m FVOLT ..
ADM239LJN ,+5 V Powered CMOS RS-232 Drivers/ReceiversAPPLICATIONS8 R2R2 9 R2OUT INComputersGNDADM232LPeripherals15ModemsPrinters *INTERNAL 400kW PULL-UP ..
ADM239LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversAPPLICATIONS8 R2R2 9 R2OUT INComputersGNDADM232LPeripherals15ModemsPrinters *INTERNAL 400kW PULL-UP ..
ADM239LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversFEATURESSingle 5 V Power Supply+5V INPUTMeets All EIA-232-E and V.28
AD7854AQ-AD7854AR-AD7854ARS-AD7854LAR-AD7854LARS
3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs
FUNCTIONAL BLOCK DIAGRAMREV.B
3 V to 5 V Single Supply, 200 kSPS
12-Bit Sampling ADCs
FEATURES
Specified for VDD of 3V to 5.5V
Read-Only Operation
AD7854–200 kSPS; AD7854L–100 kSPS
System and Self-Calibration
Low Power
Normal Operation
AD7854:15mW (VDD = 3 V)
AD7854L:5.5mW (VDD = 3 V)
Automatic Power-Down After Conversion (25�W)
AD7854:1.3mW 10 kSPS
AD7854L:650 �W 10 kSPS
Flexible Parallel Interface
12-Bit Parallel/8-Bit Parallel (AD7854)
28-Lead DIP, SOIC and SSOP Packages (AD7854)
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
PRODUCT HIGHLIGHTSOperation with either 3 V or 5 V power supplies.Flexible power management options including automatic
power-down after conversion. By using the power manage-
ment options a superior power performance at slower
throughput rates can be achieved:
AD7854: 1 mW typ @ 10 kSPS
AD7854L: 1 mW typ @ 20 kSPSOperates with reference voltages from 1.2 V to AVDD.Analog input ranges from 0 V to AVDD.Self-calibration and system calibration.Versatile parallel I/O port.Lower power version AD7854L.
GENERAL DESCRIPTIONThe AD7854/AD7854L is a high speed, low power, 12-bit ADC
that operates from a single 3 V or 5 V power supply, the
AD7854 being optimized for speed and the AD7854L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system calibration options to en-
sure accurate operation over time and temperature and has a
number of power-down options for low power applications.
The AD7854 is capable of 200 kHz throughput rate while the
AD7854L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7854 and AD7854L input
voltage range is 0 to VREF (unipolar) and –VREF/2 to +VREF/2,
centered at VREF/2 (bipolar). The coding is straight binary in
unipolar mode and twos complement in bipolar mode. Input
signal range is to the supply and the part is capable of convert-
ing full-power signals to 100kHz.
CMOS construction ensures low power dissipation of typically
5.4 mW for normal operation and 3.6 µW in power-down mode.
The part is available in 28-lead, 0.6 inch wide dual-in-line pack-
age (DIP), 28-lead small outline (SOIC) and 28-lead small
shrink outline (SSOP) packages.
*Patent pending.See Page 27 for data sheet index.
DC ACCURACY
ANALOG INPUT
REFERENCE INPUT/OUTPUT
LOGIC OUTPUTS
CONVERSION RATE
AD7854/AD7854L–SPECIFICATIONS1, 2
(AVDD = DVDD = +3.0V to +5.5V, REFIN/REFOUT = 2.5 V
External Reference, fCLKIN = 4 MHz (for L Version: 1.8 MHz (0�C to +70�C) and 1 MHz (–40�C to +85�C)); fSAMPLE = 200kHz (AD7854), 100kHz
(AD7854L); TA = TMIN to TMAX, unless otherwise noted.) Specifications in () apply to the AD7854L.
SYSTEM CALIBRATION
NOTESTemperature ranges as follows:A, B Versions,–40°C to +85°C; S Version, –55°C to +125°C.Specifications apply after calibration.Not production tested. Guaranteed by characterization at initial product release.Sample tested @ +25°C to ensure compliance.All digital inputs @ DGND except for CONVST @ DVDD. No load on the digital outputs. Analog inputs @ AGND.CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST @ DVDD. No load on the digital outputs. Analog inputs @ AGND.The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × VREF,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF
(unipolar mode) and VREF/2 ± 0.025 × VREF (bipolar mode)). This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
AD7854/AD7854L
AD7854/AD7854LNOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.Mark/Space ratio for the master clock input is 40/60 to 60/40.The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth applies (see Power-Down
section).Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.t9 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t9, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8MHz master clock.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1 (AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7854 and 1.8 MHz for AD7854L;
TA = TMIN to TMAX, unless otherwise noted)
ORDERING GUIDENOTESLinearity error refers to the integral linearity error.Q = Cerdip; R = SOIC; RS = SSOP.L signifies the low power version.This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for
evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards
ending in the CB designator. For more information on Analog Devices products and evaluation boards visit our
World Wide Web home page at http://.
Figure 1.Load Circuit for Digital Output Timing
Specifications
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Commercial (S Version) . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, (Soldering, 10 secs) . . . . . . . . . +300°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450mW
θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
θJC Thermal Impedance . . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device.This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied.Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latchup.
PIN CONFIGURATION
FOR DIP, SOIC AND SSOP
AD7854/AD7854L
PIN FUNCTION DESCRIPTIONS6AVDD
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7854/AD7854L, it is
defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Unipolar Offset ErrorThis is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in the unipolar mode.
Unipolar Gain ErrorThis is the deviation of the last code transition (111 . . . 110 to
111 . . . 111) from the ideal, i.e., AIN(–) +VREF/2 – 1.5 LSB,
after the unipolar offset error has been adjusted out.
Bipolar Positive Full-Scale ErrorThis applies to the bipolar modes only and is the deviation of the
last code transition from the ideal AIN(+) voltage. For bipolar
mode, the ideal AIN(+) voltage is (AIN(–) +VREF/2 – 1.5 LSB).
Negative Full-Scale ErrorThis applies to the bipolar mode only and is the deviation of the
first code transition (10 . . . 000 to 10 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – VREF/2 + 0.5 LSB).
Bipolar Zero ErrorThis is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).
Track/Hold Acquisition TimeThe track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental.Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76)dB
Thus for a 12-bit converter, this is 74dB.
AD7854/AD7854L
AD7854/AD7854L ON-CHIP REGISTERSThe AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the
AD7854/AD7854L will operate as a read-only ADC. The WR pin should be tied to DVDD for operating the AD7854/AD7854L as a
read-only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7854/AD7854L contains a control register, ADC output data register, status register, test register and 10 calibra-
tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test andcalibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip RegistersWriting
To write to the AD7854/AD7854L, a 16-bit word of data must be transferred. This transfer consists of two 8-bit writes. The first
8 bits of data that are written must consist of the 8 LSBs of the 16-bit word and the second 8 bits that are written must consist of the
8 MSBs of the 16-bit word. For each of these 8-bit writes, the data is placed on Pins DB0 to DB7, Pin DB0 being the LSB of each
transfer and Pin DB7 being the MSB of each transfer. The two MSBs of the 16-bit word, ADDR1 and ADDR0, are decoded to
determine which register is addressed, and the 14 LSBs are written to the addressed register. Table I shows the decoding of the
address bits, while Figure 2 shows the overall write register hierarchy.
Table I.Write Register AddressingReading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register. Note:when reading from the calibration registers, the low byte must always be read first.
Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register
until the read selection bits are changed in the control register.
Table II.Read Register Addressing
CONTROL REGISTERThe arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described
below. The power-up status of all bits is 0.
MSB
LSB
Control Register Bit Function Description
Table III.Calibration Selection
AD7854/AD7854L
STATUS REGISTERThe arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in
the status register are described below. The power-up status of all bits is 0.
Figure 4.Flowchart for Reading the Status Register
MSB
LSB
Status Register Bit Function Description
CALIBRATION REGISTERSThe AD7854/AD7854L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read
from all 10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the
user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration RegistersThe calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are
addressed (See Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should
not attempt to read from and write to the calibration registers at the same time.
Table IV.Calibration Register Addressing
Writing to/Reading from the Calibration RegistersWhen writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
When reading from the calibration registers a write to the con-
trol register is required to set the CALSLT0 and CALSLT1 bits
and also to set the RDSLT1 and RDSLT0 bits to 10 (this
addresses the calibration registers for reading). The calibration
register pointer is reset on writing to the control register setting
the CALSLT1 and CALSLT0 bits, or upon completion of all
the calibration register write/read operations. When reset it
points to the first calibration register in the selected write/read
sequence. The calibration register pointer points to the gain
calibration register upon reset in all but one case, this case
being where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-
bration register is being accessed, the calibration register pointer
is automatically incremented after each full calibration register
write/read operation. The calibration register address pointer is
incremented after the high byte read or write operation in byte
mode. Therefore when reading from or writing to the calibra-
tion registers, the low byte transfer must be carried out first, i.e.,
HBEN is at logic zero. The order in which the 10 calibration
registers are arranged is shown in Figure 5. Read/Write opera-
tions may be aborted at any time before all the calibration
registers have been accessed, and the next control register write
operation resets the calibration register pointer. The flowchart
in Figure 6 shows the sequence for writing to the calibration
registers. Figure 7 shows the sequence for reading from the cali-
bration registers.
When reading from the calibration registers there are always two
leading zeros for each of the registers.
Figure 6.Flowchart for Writing to the Calibration Registers
AD7854/AD7854LFigure 7. Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration RegisterThe offset calibration register contains 16 bits. The two MSBs
are zero and the 14 LSBs contain offset data. By changing the
contents of the offset register, different amounts of offset on the
analog input signal can be compensated for.Decreasing the
number in the offset calibration register compensates for nega-
tive offset on the analog input signal, and increasing the number
in the offset calibration register compensates for positive offset
on the analog input signal. The default value of the offset cali-
bration register is 0010 0000 0000 0000 approximately. This is
not the exact value, but the value in the offset register should be
close to this value. Each of the 14 data bits in the offset register
is binary weighted; the MSB has a weighting of 5% of the refer-
ence voltage, the MSB-1 has a weighting of 2.5%, the MSB-2
has a weighting of 1.25%, and so on down to the LSB which has
a weighting of 0.0006%. This gives a resolution of ±0.0006% of
VREF approximately. The resolution can also be expressed as
±(0.05 × VREF)/213 volts. This equals ±0.015 mV, with a 2.5 V
reference. The maximum offset that can be compensated for is
±5% of the reference voltage, which equates to ±125mV with a
2.5V reference and ±250 mV with a 5 V
reference.If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5V, what code needs to be written to the
offset register to compensate for the offset 2.5V reference implies that the resolution in the offset reg-
ister is 5% × 2.5 V/213 = 0.015 mV.+20 mV/0.015mV =
1310.72; rounding to the nearest number gives 1311.In
binary terms this is 00 0101 0001 1111, therefore increase
the offset register by 00 0101 0001 1111.
This method of compensating for offset in the analog input sig-
nal allows for fine tuning the offset compensation. If the offset
on the analog input signal is known, there is no need to apply
the offset voltage to the analog input pins and do a system cali-
bration. The offset compensation can take place in software.
Adjusting the Gain Calibration RegisterThe gain calibration register contains 16 bits. The two MSBs
are zero and the 14 LSBs contain gain data. As in the offset cali-
bration register the data bits in the gain calibration register are
binary weighted, with the MSB having a weighting of 2.5% of
the reference voltage. The gain register value is effectively multi-
plied by the analog input to scale the conversion result over the
full range.Increasing the gain register compensates for a
smaller analog input range and decreasing the gain register com-
pensates for a larger input range. The maximum analog input
range that the gain register can compensate for is 1.025 times
the reference voltage, and the minimum input range is 0.975
times the reference voltage.
When using the software conversion start for maximum
throughput, the user must ensure the control register write
operation extends beyond the falling edge of BUSY. The falling
edge of BUSY resets the CONVST bit to 0 and allows it to be
reprogrammed to 1 to start the next conversion.
TYPICAL CONNECTION DIAGRAMFigure 8 shows a typical connection diagram for the AD7854/
AD7854L. The AGND and the DGND pins are connected
together at the device for good noise suppression. The first
CONVST applied after power-up starts a self-calibration
sequence. This is explained in the calibration section of the data
sheet. Applying the RD and CS signals causes the conversion
result to be output on the 12 data pins. Note that after power is
applied to AVDD and DVDD, and the CONVST signal is applied,
the part requires (70 ms + 1/sample rate) for the internal refer-
ence to settle and for the self-calibration to be completed.
Figure 8. Typical Circuit
For applications where power consumption is a major concern,
the power-down options can be programmed by writing to the
part. See Power-Down section for more detail on low power
applications.
CIRCUIT INFORMATIONThe AD7854/AD7854L is a fast, 12-bit single supply A/D con-
verter. The part requires an external 4 MHz/1.8 MHz master
clock (CLKIN), two CREF capacitors, a CONVST signal to start
conversion and power supply decoupling capacitors. The part
provides the user with track/hold, on-chip reference, calibration
features, A/D converter and parallel interface logic functions on
a single chip. The A/D converter section of the AD7854/
AD7854L consists of a conventional successive-approximation
converter based around a capacitor DAC. The AD7854/
AD7854L accepts an analog input range of 0 to +VREF. VREF
can be tied to VDD. The reference input to the part connected
via a 150 kΩ resistor to the internal 2.5 V reference and to the
on-chip buffer.
A major advantage of the AD7854/AD7854L is that a conver-
sion can be initiated in software as well as applying a signal to
the CONVST pin. The part is available in a 28-Lead SSOP
package, and this offers the user considerable space saving advan-
tages over alternative solutions. The AD7854L version typically
consumes only 5.5mW making it ideal for battery-powered
applications.
CONVERTER DETAILSThe master clock for the part is applied to the CLKIN pin.
Conversion is initiated on the AD7854/AD7854L by pulsing the
CONVST input or by writing to the control register and setting
the CONVST bit to 1. On the rising edge of CONVST (or at the
end of the control register write operation), the on-chip track/
hold goes from track to hold mode. The falling edge of the CLKIN
signal which follows the rising edge of CONVST initates the
conversion, provided the rising edge of CONVST (or WR when
converting via the control register) occurs typically at least 10 ns
before this CLKIN edge. The conversion takes 16.5 CLKIN
periods from this CLKIN falling edge. If the 10 ns setup time is
not met, the conversion takes 17.5 CLKIN periods.
The time required by the AD7854/AD7854L to acquire a signal
depends upon the source resistance connected to the AIN(+)
input. Please refer to the Acquisition Time section for more
details.
When a conversion is completed, the BUSY output goes low,
and the result of the conversion can be read by accessing the
data through the data bus. To obtain optimum performance
from the part, read or write operations should not occur during
the conversion or less than 200ns prior to the next CONVST
rising edge. Reading/writing during conversion typically de-
grades the Signal to (Noise + Distortion) by less than 0.5 dBs.
The AD7854 can operate at throughput rates of over 200 kSPS
(up to 100kSPS for the AD7854L).
With the AD7854L, 100kSPS throughput can be obtained as
follows: the CLKIN and CONVST signals are arranged to give
a conversion time of 16.5 CLKIN periods as described above
and 1.5 CLKIN periods are allowed for the acquisition time.
With a 1.8 MHz clock, this gives a full cycle time of 10 µs,
which equates to a throughput rate of 100 kSPS.
AD7854/AD7854LFigure 10.THD vs. Analog Input Frequency
The maximum source impedance depends on the amount of
total harmonic distortion (THD) that can be tolerated. The
THD increases as the source impedance increases. Figure 10
shows a graph of the total harmonic distortion vs. analog input
signal frequency for different source impedances. With the
setup as in Figure 11, the THD is at the –90dB level. With a
source impedance of 1kΩ and no capacitor on the AIN(+) pin,
the THD increases with frequency.
In a single supply application (both 3 V and 5 V), the V+ and
V– of the op amp can be taken directly from the supplies to the
AD7854/AD7854L which eliminates the need for extra external
power supplies. When operating with rail-to-rail inputs and out-
puts at frequencies greater than 10 kHz, care must be taken in
selecting the particular op amp for the application. In particular,
for single supply applications the input amplifiers should be
connected in a gain of –1 arrangement to get the optimum per-
formance. Figure 11 shows the arrangement for a single supply
application with a 50 Ω and 10 nF low-pass filter (cutoff fre-
quency 320 kHz) on the AIN(+) pin. Note that the 10nF is a
capacitor with good linearity to ensure good ac performance.
Recommended single supply op amps are the AD820 and the
AD820-3V.
Figure 11.Analog Input Buffering
ANALOG INPUTThe equivalent analog input circuit is shown in Figure 9. Dur-
ing the acquisition interval the switches are both in the track
position and the AIN(+) charges the 20 pF capacitor through
the 125 Ω resistance. On the rising edge of CONVST switches
SW1 and SW2 go into the hold position retaining charge on thepF capacitor as a sample of the signal on AIN(+). The
AIN(–) is connected to the 20 pF capacitor, and this unbalances
the voltage at Node A at the input of the comparator. The
capacitor DAC adjusts during the remainder of the conversion
cycle to restore the voltage at Node A to the correct value. This
action transfers a charge, representing the analog input signal, to
the capacitor DAC which in turn forms a digital representation
of the analog input signal. The voltage on the AIN(–) pin directly
influences the charge transferred to the capacitor DAC at the
hold instant. If this voltage changes during the conversion period,
the DAC representation of the analog input voltage is altered.
Therefore it is most important that the voltage on the AIN(–)
pin remains constant during the conversion period. Further-
more, it is recommended that the AIN(–) pin is always connected
to AGND or to a fixed dc voltage.
Figure 9.Analog Input Equivalent Circuit
Acquisition TimeThe track-and-hold amplifier enters its tracking mode on the
falling edge of the BUSY signal. The time required for the
track-and-hold amplifier to acquire an input signal depends on
how quickly the 20 pF input capacitance is charged. There is a
minimum acquisition time of 400 ns. For large source imped-
ances, >2 kΩ, the acquisition time is calculated using the formula:
tACQ = 9 × (RIN + 125 Ω) × 20 pF
where RIN is the source impedance of the input signal, and
125Ω, 20 pF is the input R, C.
DC/AC ApplicationsFor dc applications, high source impedances are acceptable,
provided there is enough acquisition time between conversions
to charge the 20 pF capacitor. For example with RIN = 5 kΩ,
the required acquisition time is 922ns.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the AIN(+) pin, as shown in Figure 11. In applica-
tions where harmonic distortion and signal to noise ratio are
critical, the analog input should be driven from a low impedance
source.Large source impedances significantly affect the ac per-
formance of the ADC. They may require the use of an input
buffer amplifier. The choice of the amplifier is a function of the
particular application.
