AD7853AR ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsGENERAL DESCRIPTIONSM1 SM2 SYNC DIN DOUT SCLK POLARITYThe AD7853/AD7853L are high speed, low power, ..
AD7853ARS ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsFEATURESSpecified for V of 3 V to 5.5 VDDAV AGND AGNDDDRead-Only OperationAD7853–200 kSPS; AD7853L– ..
AD7853BR ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsSpecifications in () apply to the AD7853L.A MIN MAX1 1Parameter A Version B Version Units Test Cond ..
AD7853LAN ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsSPECIFICATIONSDD DD IN OUTExternal Reference, f = 4 MHz (1.8 MHz B Grade (08C to +708C), 1 MHz A an ..
AD7853LAR ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsfeatures a pseudo-6. Self- and system calibration.differential sampling scheme. The AD7853/AD7853L ..
AD7853LBN ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs3 V to 5 V Single Supply, 200 kSPSa12-Bit Sampling ADCsAD7853/AD7853L*FUNCTIONAL BLOCK DIAGRAM
ADM238LJN ,+5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION All members of the ADM230L family, except the ADM231LThe ADM2xx family of line ..
ADM238LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications120 kB/s Data Rate1 16C1+ +5V TO +10V VCCOn-Board DC-DC Converters 1m F 1m F 1m FVOLT ..
ADM238LJR-REEL , 5 V-Powered CMOS RS-232 Drivers/Receivers
ADM239LAN ,+5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION All members of the ADM230L family, except the ADM231LThe ADM2xx family of line ..
ADM239LAR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications120 kB/s Data Rate1 16C1+ +5V TO +10V VCCOn-Board DC-DC Converters 1m F 1m F 1m FVOLT ..
ADM239LJN ,+5 V Powered CMOS RS-232 Drivers/ReceiversAPPLICATIONS8 R2R2 9 R2OUT INComputersGNDADM232LPeripherals15ModemsPrinters *INTERNAL 400kW PULL-UP ..
AD7853AN-AD7853AR-AD7853ARS-AD7853BR-AD7853LAN-AD7853LAR-AD7853LBN
3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs
FUNCTIONAL BLOCK DIAGRAM
AVDDAGND
DVDD
DGND
CLKIN
CONVST
BUSY
SLEEPCAL
CREF2
CREF1
REFIN/
REFOUT
AIN(–)
AIN(+)
AMODE
SM1SCLKSYNCPOLARITYDOUTDINSM2
AGNDREV.B
3 V to 5 V Single Supply, 200 kSPS
12-Bit Sampling ADCs
FEATURES
Specified for VDD of 3V to 5.5V
Read-Only Operation
AD7853–200 kSPS; AD7853L–100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
Low Power:
AD7853:12mW (VDD = 3 V)
AD7853L:4.5mW (VDD = 3 V)
Automatic Power Down After Conversion (25mW)
Flexible Serial Interface:
8051/SPI™/QSPI™/mP Compatible
24-Lead DIP, SOIC and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
GENERAL DESCRIPTIONThe AD7853/AD7853L are high speed, low power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the
AD7853 being optimized for speed and the AD7853L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system-calibration options to en-
sure accurate operation over time and temperature and have a
number of power-down options for low power applications.
The part powers up with a set of default conditions and can
operate as a read only ADC.
The AD7853 is capable of 200kHz throughput rate while the
AD7853L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500ns and features a pseudo-
differential sampling scheme. The AD7853/AD7853L voltage
range is 0 to VREF with both straight binary and twos comple-
ment output coding. Input signal range is to the supply, and the
part is capable of converting full power signals to 100kHz.
CMOS construction ensures low power dissipation of typically
4.5mW for normal operation and 1.15 mW in power-down
mode, with a throughput rate of 10kSPS (VDD = 3V). The part
is available in 24-lead, 0.3 inch wide dual-in-line package
(DIP), 24-lead small outline (SOIC) and 24-lead small shrink
outline (SSOP) packages.
PRODUCT HIGHLIGHTSSpecified for 3 V and 5 V supplies.Automatic calibration on power-up.Flexible power management options including automatic
power-down after conversion.Operates with reference voltages from 1.2 V to VDD.Analog input ranges from 0 V to VDD.Self- and system calibration.Versatile serial I/O port (SPI/QSPI/8051/mP).Lower power version AD7853L.
*Patent pending.
SPI and QSPI are trademarks of Motorola, Incorporated.
ANALOG INPUT
REFERENCE INPUT/OUTPUT
AD7853/AD7853L–SPECIFICATIONS1, 2
(AVDD = DVDD = +3.0V to +5.5V, REFIN/REFOUT = 2.5 V
External Reference, fCLKIN = 4 MHz (1.8MHz B Grade (08C to +708C), 1 MHz A and B Grades (–408C to +858C) for L Version); fSAMPLE = 200kHz
(AD7853) 100kHz (AD7853L); SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted.) Specifications in () apply to the AD7853L.
CONVERSION RATE
NOTESTemperature ranges as follows:A, B Versions,–40°C to +85°C. For L Versions, A and B Versions fCLKIN = 1 MHz over –40°C to +85°C temperature range,
B Version fCLKIN = 1.8 MHz over 0°C to +70°C temperature range.Specifications apply after calibration.SNR calculation includes distortion and noise components.Sample tested @ +25°C to ensure compliance.All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.
Analog inputs @ AGND.The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7853/AD7853L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) –0.05 · VREF,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF – 0.025 · VREF).
This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
AD7853/AD7853L
AD7853/AD7853L
TIMING SPECIFICATIONS1NOTES
Descriptions that refer to SCLK› (rising) or SCLKfl (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of
SCLK will apply.Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.Mark/Space ratio for the master clock input is 40/60 to 60/40.For Interface Modes 1, 2, 3 the SCLK max frequency will be 4 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be fCLKIN.The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply (see Power-
Down section).Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 tSCLK = 0.5 tCLKIN.t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part
in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1MHz master clock.
Specifications subject to change without notice.
(AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7853 and 1.8/1 MHz for AD7853L; TA = TMIN to
TMAX, unless otherwise noted)
TYPICAL TIMING DIAGRAMSFigures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In-
terface Modes 2 and 3. To attain the maximum sample rate of
100 kHz (AD7853L) or 200 kHz (AD7853) in Interface Modes
2 and 3, reading and writing must be performed during conver-
sion. Figure 3 shows the timing diagram for Interface Modes 4
and 5 with sample rate of 100 kHz (AD7853L) or 200 kHz
(AD7853). At least 400ns acquisition time must be allowed
(the time from the falling edge of BUSY to the next rising edge
of CONVST) before the next conversion begins to ensure that
the part is settled to the 12-bit level. If the user does not want to
provide the CONVST signal, the conversion can be initiated in
software by writing to the control register.
TO OUTPUT
PIN+2.1V
1.6mA
IOL
100pFFigure 1.Load Circuit for Digital Output Timing
Specifications
POLARITY PIN LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
BUSY (O/P)
CONVST (I/P)
DOUT (O/P)
STATEFigure 2.AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
Figure 3.AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
AD7853/AD7853L
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . –10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/WJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450mWJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)JC Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >3 kV
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device.This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied.Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDENOTESLinearity error refers to the integral linearity error.N = Plastic DIP; R = SOIC; RS = SSOP.L signifies the low power version.This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with
all Analog Devices, Inc. evaluation boards ending in the CB designators.
PIN CONFIGURATIONS
DIP, SOIC AND SSOP
CAL
SCLK
SM2
SLEEP
REFIN/REFOUT
BUSY
AIN(+)
AVDD
AGND
CREF1
CREF2
AIN(–)
CONVST
DVDD
SYNC
CLKIN
DIN
DOUT
DGND
AMODE
POLARITY
SM1
AGND
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
AD7853/AD7853L
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7853/AD7853L, it is
defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Unadjusted ErrorThis is the deviation of the actual code from the ideal code
taking all errors into account (Gain, Offset, Integral Nonlinearity,
and other errors) at any point along the transfer function.
Unipolar Offset ErrorThis is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in the unipolar mode.
Positive Full-Scale ErrorThis applies to the unipolar and bipolar modes and is the devia-
tion of the last code transition from the ideal AIN(+) voltage
(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been
adjusted out.
Negative Full-Scale ErrorThis applies to the bipolar mode only and is the deviation of the
first code transition (10 . . . 000 to 10 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – VREF/2 + 0.5 LSB).
Bipolar Zero ErrorThis is the deviation of the midscale transition (all 1s to all 0s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).
Track/Hold Acquisition TimeThe track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within –1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental.Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N +1.76)dB
Thus for a 12-bit converter, this is 74dB.
ON-CHIP REGISTERSThe AD7853/AD7853L powers up with a set of default conditions, and the user need not ever write to the device. In this case the
AD7853/AD7853L will operate as a Read-Only ADC. The AD7853/AD7853L still retains the flexibility for performing a full power-
down, and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7853/AD7853L as a Read-
Only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7853/AD7853L contains a Control register, ADC output data register, Status register, Test register and 10 Calibra-
tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test andcalibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
WritingA write operation to the AD7853/AD7853L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine
which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are writ-
ten that the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the over-
all write register hierarchy.
Table I.Write Register Addressing
ReadingTo read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register
until the read selection bits are changed in the control register.
Table II.Read Register Addressing
AD7853/AD7853L
CONTROL REGISTERThe arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described
below. The power-up status of all bits is 0.
MSB
LSB
Control Register Bit Function Descriptions
Table III.Calibration Selection
STATUS REGISTERThe arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
STARTFigure 6.Flowchart for Reading the Status Register
MSB
LSB
Status Register Bit Function Descriptions
AD7853/AD7853L
CALIBRATION REGISTERSThe AD7853/AD7853L has ten calibration registers in all, eight for the DAC, one for the offset and one for gain. Data can be writ-
ten to or read from all ten calibration registers. In self- and system calibration the part automatically modifies the calibration regis-
ters; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration
registers.
Addressing the Calibration RegistersThe calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-
dressed (See Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should
not attempt to read from and write to the calibration registers at the same time.
Table IV. Calibration Register Addressing
Writing to/Reading from the Calibration RegistersFor writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
For reading from the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits,
but also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-
dresses the calibration registers for reading). The calibration
register pointer is reset on writing to the control register setting
the CALSLT1 and CALSLT0 bits, or upon completion of all
the calibration register write/read operations. When reset it
points to the first calibration register in the selected write/read
sequence. The calibration register pointer will point to the gain
calibration register upon reset in all but one case, this case
being where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one calibra-
tion register is being accessed, the calibration register pointer
will be automatically incremented after each calibration register
write/read operation. The order in which the ten calibration
registers are arranged is shown in Figure 7. The user may abort
at any time before all the calibration register write/read opera-
tions are completed, and the next control register write opera-
tion will reset the calibration register pointer. The flowchart in
Figure 8 shows the sequence for writing to the calibration regis-
ters and Figure 9 for reading.
CALIBRATION REGISTERS
(1)
(2)
(3)
(10)
CALIBRATION REGISTER ADDRESS POINTER POSITION IS
DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS
ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.Figure 7.Calibration Register Arrangement
When reading from the calibration registers there will always be
two leading zeros for each of the registers. When operating in
serial Interface Mode 1, the read operations to the calibration
registers cannot be aborted. The full number of read operations
must be completed (see section on serial Interface Mode 1 tim-
ing for more detail).
STARTFigure 8.Flowchart for Writing to the Calibration Registers
YES
STARTFigure 9. Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration RegisterThe offset calibration register contains 16 bits, two leading zeros
and 14 data bits. By changing the contents of the offset register,
different amounts of offset on the analog input signal can be
compensated for.Increasing the number in the offset calibra-
tion register compensates for negative offset on the analog input
signal, and decreasing the number in the offset calibration regis-
ter compensates for positive offset on the analog input signal.
The default value of the offset calibration register is 0010 0000
0000 0000 approximately. This is not an exact value, but the
value in the offset register should be close to this value. Each of
the 14 data bits in the offset register is binary weighted; the
MSB has a weighting of 5% of the reference voltage, the MSB-1
has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%,
and so on down to the LSB, which has a weighting of 0.0006%.
This gives a resolution of –0.0006% of VREF approximately.
More accurately the resolution is –(0.05 · VREF)/213 volts =0.015 mV, with a 2.5 V reference. The maximum offset that
can be compensated for is –5% of the reference voltage, which
equates to –125mV with a 2.5V reference and –250 mV with a
5 V reference.If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5V, what code needs to be written to the
offset register to compensate for the offset 2.5V reference implies that the resolution in the offset
register is 5% · 2.5 V/213 = 0.015 mV.+20 mV/0.015mV
= 1310.72; rounding to the nearest number gives 1311.In
binary terms this is 0101 0001 1111, therefore decrease the
offset register by 0101 0001 1111.
This method of compensating for offset in the analog input
signal allows for fine tuning the offset compensation. If the
offset on the analog input signal is known, there will be no need
to apply the offset voltage to the analog input pins and do a
system calibration. The offset compensation can take place in
software.
Adjusting the Gain Calibration RegisterThe gain calibration register contains 16 bits, two leading 0s
and 14 data bits. The data bits are binary weighted as in the
offset calibration register. The gain register value is effectively
multiplied by the analog input to scale the conversion result
over the full range.Increasing the gain register compensates for
a smaller analog input range and decreasing the gain register
compensates for a larger input range. The maximum analog
input range that the gain register can compensate for is 1.025
times the reference voltage, and the minimum input range is
0.975 times the reference voltage.
AD7853/AD7853Ledge of CONVST occurs at least 10 ns typically before this
CLKIN edge.The conversion cycle will take 16.5 CLKIN
periods from this CLKIN falling edge. If the 10 ns setup time is
not met, the conversion will take 17.5 CLKIN periods. The
maximum specified conversion time is 4.6 ms for the AD7853
(18 tCLKIN, CLKIN = 4 MHz) and 10 ms for the AD7853L (18
tCLKIN, CLKIN = 1.8 MHz). When a conversion is completed,
the BUSY output goes low, and then the result of the conver-
sion can be read by accessing the data through the serial inter-
face. To obtain optimum performance from the part, the read
operation should not occur during the conversion or 400␣ns
prior to the next CONVST rising edge. However, the maximum
throughput rates are achieved by reading/writing during conver-
sion, and reading/writing during conversion is likely to degrade
the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7853
can operate at throughput rates up to 200 kHz, 100kHz for
the AD7853L. For the AD7853/AD7853L a conversion takes
18 CLKIN periods, 2 CLKIN periods are needed for the
acquisition time giving a full cycle time of 5 ms (= 200 kHz,
CLKIN = 4MHz). For the AD7853L 100kHz throughput can
be obtained as follows: the CLKIN and CONVST signals are
arranged to give a conversion time of 16.5 CLKIN periods as
described above, 1.5 CLKIN periods are allowed for the acqui-
sition time. This gives a full cycle time of 10 ms (= 100 kHz,
CLKIN = 1.8 MHz). When using the software conversion start
for maximum throughput, the user must ensure the control register
write operation extends beyond the falling edge of BUSY. The
falling edge of BUSY resets the CONVST bit to 0 and allows it to
be reprogrammed to 1 to start the next conversion.
CIRCUIT INFORMATIONThe AD7853/AD7853L is a fast, 12-bit single supply A/D con-
verter. The part requires an external 4 MHz/1.8 MHz master
clock (CLKIN), two CREF capacitors, a CONVST signal to start
conversion and power supply decoupling capacitors. The part
provides the user with track/hold, on-chip reference, calibration
features, A/D converter and serial interface logic functions on a
single chip. The A/D converter section of the AD7853/AD7853L
consists of a conventional successive-approximation converter
based around a capacitor DAC. The AD7853/AD7853L accepts
an analog input range of 0 to +VDD where the reference can be
tied to VDD. The reference input to the part is buffered on-chip.
A major advantage of the AD7853/AD7853L is that a conver-
sion can be initiated in software as well as applying a signal to
the CONVST pin. Another innovative feature of the AD7853/
AD7853L is self-calibration on power-up, which is initiated
having a capacitor from the CAL pin to AGND, to give superior
dc accuracy (See Automatic Calibration on Power-Up section).
The part is available in a 24-lead SSOP package, which offers
the user considerable space-saving advantages over alternative
solutions. The AD7853L version typically consumes only 5.5mW,
making it ideal for battery-powered applications.
CONVERTER DETAILSThe master clock for the part must be applied to the CLKIN
pin. Conversion is initiated on the AD7853/AD7853L by puls-
ing the CONVST input or by writing to the control register and
setting the CONVST bit to 1. On the rising edge of CONVST
(or at the end of the control register write operation), the on-
chip track/hold goes from track to hold mode. The falling edge
of the CLKIN signal which follows the rising edge of the edge of
CONVST signal initiates the conversion, provided the rising
DC/AC ApplicationsFor dc applications high source impedances are acceptable,
provided there is enough acquisition time between conversions
to charge the 20 pF capacitor. The acquisition time can be
calculated from the above formula for different source imped-
ances. For example with RIN = 5 kW, the required acquisition
time will be 922ns.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the AIN(+) pin, as shown in Figure 13. In applica-
tions where harmonic distortion and signal to noise ratio are
critical, the analog input should be driven from a low impedance
source. Large source impedances will significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp will be a func-
tion of the particular application.
When no amplifier is used to drive the analog input the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will degrade.
Figure 12 shows a graph of the Total Harmonic Distortion vs.
analog input signal frequency for different source impedances.
With the setup as in Figure 13, the THD is at the –90dB level.
With a source impedance of 1kW and no capacitor on the AIN(+)
pin, the THD increases with frequency.
INPUT FREQUENCY – kHz
THD – dB406080
–88Figure 12.THD vs. Analog Input Frequency
In a single supply application (both 3 V and 5 V), the V+ and
V– of the op amp can be taken directly from the supplies to the
AD7853/AD7853L which eliminates the need for extra external
power supplies. When operating with rail-to-rail inputs and
outputs at frequencies greater than 10 kHz, care must be taken
in selecting the particular op amp for the application. In particu-
lar, for single supply applications the input amplifiers should be
connected in a gain of –1 arrangement to get the optimum per-
formance. Figure 13 shows the arrangement for a single supply
application with a 50 W and 10 nF low-pass filter (cutoff fre-
quency 320 kHz) on the AIN(+) pin. Note that the 10nF is a
capacitor with good linearity to ensure good ac performance.
Recommended single supply op amps are the AD820 and the
TYPICAL CONNECTION DIAGRAMFigure 10 shows a typical connection diagram for the AD7853/
AD7853L. The DIN line is tied to DGND so that no data is
written to the part. The AGND and the DGND pins are con-
nected together at the device for good noise suppression. The
CAL pin has a 0.01 mF capacitor to enable an automatic self-
calibration on power-up. The SCLK and SYNC are configured
as outputs by having SM1 and SM2 at DVDD. The conversion
result is output in a 16-bit word with four leading zeros followed
by the MSB of the 12-bit result. Note that after the AVDD and
DVDD power-up, the part will require approximately 150 ms for
the internal reference to settle and for the automatic calibration
on power-up to be completed.
For applications where power consumption is a major concern,
the SLEEP pin can be connected to DGND. See Power-Down
section for more detail on low power applications.
ANALOG INPUTThe equivalent circuit of the analog input section is shown in
Figure 11. During the acquisition interval the switches are both
in the track position and the AIN(+) charges the 20 pF capaci-
tor through the 125 W resistance. On the rising edge of CONVST
switches SW1 and SW2 go into the hold position retaining
charge on the 20pF capacitor as a sample of the signal on
AIN(+). The AIN(–) is connected to the 20 pF capacitor, and
this unbalances the voltage at Node A at the input of the com-
parator. The capacitor DAC adjusts during the remainder of the
conversion cycle to restore the voltage at Node A to the correct
value. This action transfers a charge, representing the analog
input signal, to the capacitor DAC which in turn forms a digital
representation of the analog input signal. The voltage on the
AIN(–) pin directly influences the charge transferred to the
capacitor DAC at the hold instant. If this voltage changes dur-
ing the conversion period, the DAC representation of the analog
input voltage will be altered. Therefore it is most important that
the voltage on the AIN(–) pin remains constant during the con-
version period. Furthermore, it is recommended that the AIN(–)
pin is always connected to AGND or to a fixed dc voltage.
AIN(+)
AIN(–)
125V
TRACK
HOLD
CREF2
125V
SW1Figure 11.Analog Input Equivalent Circuit
Acquisition TimeThe track and hold amplifier enters its tracking mode on the
falling edge of the BUSY signal. The time required for the track
and hold amplifier to acquire an input signal will depend on
how quickly the 20 pF input capacitance is charged. The acqui-
sition time is calculated using the formula:
tACQ = 9 · (RIN + 125 W) · 20 pF
AD7853/AD7853LFigure 15.–VREF/2 about VREF/2 Bipolar Input Configuration
+FS–1LSB
OUTPUT
CODE
VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE
1LSBFigure 16.Unipolar Transfer Characteristic
Figure 15 shows the AD7853/AD7853L’s –VREF/2 bipolar ana-
log input configuration (where AIN(+) cannot go below 0 V so
for the full bipolar range then the AIN(–) pin should be biased
to +VREF/2). Once again the designed code transitions occur
midway between successive integer LSB values. The output
coding is twos complement with 1 LSB = 4096 = 3.3 V/4096 =
0.8 mV. The ideal input/output transfer characteristic is shown
in Figure 17.
OUTPUT
CODE
VREF/2
VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE
111...111Figure 17.Bipolar Transfer Characteristic
Figure 13.Analog Input Buffering
Input RangesThe analog input range for the AD7853/AD7853L is 0 V to
VREF in both the unipolar and bipolar ranges.
The only difference between the unipolar range and the bipolar
range is that in the bipolar range the AIN(–) has to be biased up
to +VREF/2 and the output coding is twos complement (See
Table V and Figures 14 and 15). The unipolar or bipolar mode
is selected by the AMODE pin (0 for the unipolar range and 1
for the bipolar range).
Table V.Analog Input ConnectionsNOTESOutput code format is straight binary.Range is –VREF/2 biased about VREF/2. Output code format is twos complement.
Note that the AIN(–) pin on the AD7853/AD7853L can be
biased up above AGND in the unipolar mode also, if required.
The advantage of biasing the lower end of the analog input
range away from AGND is that the user does not have to have
the analog input swing all the way down to AGND. This has the
advantage in true single supply applications that the input am-
plifier does not have to swing all the way down to AGND. The
upper end of the analog input range is shifted up by the same
amount. Care must be taken so that the bias applied does not
shift the upper end of the analog input above the AVDD supply.
In the case where the reference is the supply, AVDD, the AIN(–)
must be tied to AGND in unipolar mode.
Figure 14.0 to VREF Unipolar Input Configuration
Transfer FunctionsFor the unipolar range the designed code transitions occur
midway between successive integer LSB values (i.e., 1/2 LSB,
3/2LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is
REFERENCE SECTIONFor specified performance, it is recommended that when using
an external reference this reference should be between 2.3 V
and the analog supply AVDD. The connections for the relevant
reference pins are shown in the typical connection diagrams. If
the internal reference is being used, the REFIN/REFOUT pin
should have a 100nF capacitor connected to AGND very close
to the REFIN/REFOUT pin. These connections are shown in
Figure 18.
If the internal reference is required for use external to the ADC,
it should be buffered at the REFIN/REFOUT pin and a 100 nF
connected from this pin to AGND. The typical noise performance
for the internal reference, with 5V supplies is 150nV/√Hz @kHz and dc noise is 100 mV p-p.
AVDDDVDD
CREF1
CREF2
REFIN/REFOUT
ANALOG SUPPLY
+3V TO +5V
0.1mF
0.01mF
0.1mF
AD7853/AD7853LFigure 18.Relevant Connections When Using Internal
Reference
The other option is that the REFIN/REFOUT pin be overdriven
by connecting it to an external reference. This is possible due to
the series resistance from the REFIN/REFOUT pin to the internal
reference. This external reference can have a range that includes
AVDD.When using AVDD as the reference source, the 100nF
capacitor from the REFIN/REFOUT pin to AGND should be as
close as possible to the REFIN/REFOUT pin, and also the CREF1
pin should be connected to AVDD to keep this pin at the same
level as the reference.The connections for this arrangement are
shown in Figure 19. When using AVDD it may be necessary to
add a resistor in series with the AVDD supply. This will have the
effect of filtering the noise associated with the AVDD supply.
ANALOG SUPPLY
+3V TO +5V
10mF
0.1mF
PERFORMANCE CURVESFigure 20 shows a typical FFT plot for the AD7853 at 200 kHz
sample rate and 10 kHz input frequency.
FREQUENCY – kHz
SNR – dBFigure 20.FFT Plot
Figure 21 shows the SNR versus Frequency for different sup-
plies and different external references.
INPUT FREQUENCY – kHz100
S(N+D) RATIO – dB406080Figure 21.SNR vs. Frequency
Figure 22 shows the Power Supply Rejection Ratio versus Fre-
quency for the part. The Power Supply Rejection Ratio is de-
fined as the ratio of the power in ADC output at frequency f to
the power of a full-scale sine wave.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power of a full-
scale sine wave. Here a 100 mV peak-to-peak sine wave is
coupled onto the AVDD supply while the digital supply is left
unaltered. Both the 3.3 V and 5.0 V supply performances are
shown.
