AD7851AN-AD7851AR-AD7851ARS-AD7851KN-AD7851KR Fast Delivery |IC PHOENIX CO.,LIMITED

AD7851KN ,14-Bit 333 kSPS Serial A/D ConverterGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD7851 is a high speed, 14-bit ADC that operates from a 1 ..
AD7851KR ,14-Bit 333 kSPS Serial A/D ConverterAPPLICATIONSCALIBRATIONCAL MEMORYDigital Signal ProcessingAND CONTROLLERSpeech Recognition and Synt ..
AD7853AN ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsSpecifications apply after calibration.3SNR calculation includes distortion and noise components.4S ..
AD7853AR ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsGENERAL DESCRIPTIONSM1 SM2 SYNC DIN DOUT SCLK POLARITYThe AD7853/AD7853L are high speed, low power, ..
AD7853ARS ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsFEATURESSpecified for V of 3 V to 5.5 VDDAV AGND AGNDDDRead-Only OperationAD7853–200 kSPS; AD7853L– ..
AD7853BR ,3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCsSpecifications in () apply to the AD7853L.A MIN MAX1 1Parameter A Version B Version Units Test Cond ..
ADM238LAR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications120 kB/s Data Rate1 16C1+ +5V TO +10V VCCOn-Board DC-DC Converters 1m F 1m F 1m FVOLT ..
ADM238LJN ,+5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION All members of the ADM230L family, except the ADM231LThe ADM2xx family of line ..
ADM238LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications120 kB/s Data Rate1 16C1+ +5V TO +10V VCCOn-Board DC-DC Converters 1m F 1m F 1m FVOLT ..
ADM238LJR-REEL , 5 V-Powered CMOS RS-232 Drivers/Receivers
ADM239LAN ,+5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION All members of the ADM230L family, except the ADM231LThe ADM2xx family of line ..
ADM239LAR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications120 kB/s Data Rate1 16C1+ +5V TO +10V VCCOn-Board DC-DC Converters 1m F 1m F 1m FVOLT ..

AD7851AN-AD7851AR-AD7851ARS-AD7851KN-AD7851KR
14-Bit 333 kSPS Serial A/D Converter
REV.A
FUNCTIONAL BLOCK DIAGRAM
14-Bit 333 kSPS
Serial A/D Converter
FEATURES
Single 5 V Supply
333 kSPS Throughput Rate/62 LSB DNL—A Grade
285 kSPS Throughput Rate/61 LSB DNL—K Grade
A & K Grades Guaranteed to 1258C/238 kSPS
Throughput Rate
Pseudo-Differential Input with Two Input Ranges
System and Self-Calibration with Autocalibration on
Power-Up
Read/Write Capability of Calibration Data
Low Power:60 mW typ
Power-Down Mode:5 mW typ Power Consumption
Flexible Serial Interface:
8051/SPI/QSPI/ mP Compatible
24-Pin DIP, SOIC and SSOP Packages
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
Instrumentation and Control Systems
High Speed Modems
Automotive
GENERAL DESCRIPTION
The AD7851 is a high speed, 14-bit ADC that operates from a
single 5 V power supply. The ADC powers-up with a set of
default conditions at which time it can be operated as a read-
only ADC. The ADC contains self-calibration and system-
calibration options to ensure accurate operation over time and
temperature and has a number of power-down options for low
power applications.
The AD7851 is capable of 333 kHz throughput rate. The input
track-and-hold acquires a signal in 0.33 μs and features a
pseudo-differential sampling scheme. The AD7851 has the
added advantage of two input voltage ranges (0 V to VREF, and
–VREF/2 to +VREF/2 centered about VREF/2). Input signal range
is to VDD and the part is capable of converting full-power signals
to 20 MHz.
CMOS construction ensures low power dissipation (60 mW typ)
with power-down mode (5 μW typ). The part is available in 24-
pin, 0.3 inch-wide dual-in-line package (DIP), 24-lead small
outline (SOIC) and 24-lead small shrink outline (SSOP) packages.
*Patent pending.
See Page 35 for data sheet index.
PRODUCT HIGHLIGHTSSingle 5 V supply.Operates with reference voltages from 4 V to VDD.Analog input ranges from 0 V to VDD.System and self-calibration including power-down mode.Versatile serial I/O port.
AD7851–SPECIFICATIONS1, 2A Grade: fCLKIN = 7 MHz (–408C to +858C), fSAMPLE = 333kHz; K Grade: fCLKIN = 6 MHz
(08C to +858C), fSAMPLE = 285 kHz; A and K Grade: fCLKIN = 5 MHz (to +1258C), fSAMPLE =
238 kHz; (AVDD = DVDD = +5.0 V 6 5%, REFIN/REFOUT = 4.096 V External Reference; SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted)
ANALOG INPUT
REFERENCE INPUT/OUTPUT
LOGIC INPUTS
AD7851
SYSTEM CALIBRATION
NOTESTemperature ranges as follows:A Version, –40°C to +125°C; K Version,0°C to +125°C.Specifications apply after calibration.SNR calculation includes distortion and noise components.Sample tested @ +25°C to ensure compliance.All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.
Analog inputs @ AGND.The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × VREF, and the
allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF). This is
explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
AD7851
fSCLK
t10
t11
t11A
t12
tCAL
NOTES
Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of
SCLK will apply.Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.Mark/Space ratio for the master clock input is 40/60 to 60/40.For Interface Modes 1, 2, 3 the SCLK max frequency will be 10 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be fCLKIN.The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-
Down section).Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 tSCLK = 0.5 tCLKIN.t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in
turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.The typical time specified for the calibration times is for a master clock of 6 MHz.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1 (AVDD = DVDD = +5.0 V 6 5%; fCLKIN = 6 MHz, TA = TMIN to TMAX, unless otherwise noted)
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In-
terface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia-
gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least 330ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the CONVST signal, the conversion can be initiated in software
by writing to the control register.
+2.1V
200µA
50pF
OUTPUT
PIN
IOH
Figure 1.Load Circuit for Digital Output Timing
Specifications
POLARITY PIN LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
BUSY (O/P)
CONVST (I/P)
t10
DOUT (O/P)
DIN (I/P)3-STATE
Figure 2.AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
SYNC (O/P)
SCLK (O/P)
BUSY (O/P)
CONVST (I/P)
t10
DOUT (O/P)DB0DB11
DIN (I/P)
AD7851
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A, K Versions) . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W
Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . +260°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450mW
θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
θJC Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device.This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied.Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
PINOUT FOR DIP, SOIC AND SSOP
CONVST
BUSY
SLEEP
REFIN/REFOUT
AVDD
AGND
CREF1
CREF2
AIN(+)
AIN(–)
AGND
SYNC
SCLK
CLKIN
DIN
DOUT
DGND
DVDD
CAL
SM2
SM1
POLARITY
AMODE
ORDERING GUIDE1
NOTESBoth A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238kHz (5 MHz)..Linearity error refers to the integral linearity error.N = Plastic DIP; R = SOIC; RS = SSOP.This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration
purposes.This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the
CB designators.
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Unadjusted Error
This is the deviation of the actual code from the ideal code tak-
ing all errors into account (Gain, Offset, Integral Nonlinearity,
and other errors) at any point along the transfer function.
Unipolar Offset Error
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in the unipolar mode.
Positive Full-Scale Error
This applies to the unipolar and bipolar modes and is the devia-
tion of the last code transition from the ideal AIN(+) voltage
(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been
adjusted out.
Negative Full-Scale Error
This applies to the bipolar mode only and is the deviation of the
first code transition (00 . . . 000 to 00 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – VREF/2 + 0.5 LSB).
Bipolar Zero Error
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental.Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N +1.76)dB
Thus for a 14-bit converter, this is 86dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7851, it is defined as:
THD(dB)=20log
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
Power Supply Rejection Ratio
Power Supply Rejection Ratio (PSRR) is defined as the ratio of
the power in ADC output at frequency f to the power of the full-
scale sine wave applied to the supply voltage (VDD). The units
are in LSB, %of FS per % of supply voltage, or expressed loga-
rithmically, in dB (PSRR (dB) = 10 log(Pf/Pfs)).
Full Power Bandwidth
The Full Power Bandwidth (FPBW) is that frequency at which
the amplitude of the reconstructed (using FFTs) fundamental
(neglecting harmonics and SNR) is reduced by 3 dB for a full-
scale input.
AD7851
PIN FUNCTION DESCRIPTION
AD7851 ON-CHIP REGISTERS
The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7851 will
operate as a Read-Only ADC. The AD7851 still retains the flexibility for performing a full power-down, and a full self-calibration.
Note that the DIN pin should be tied to DGND for operating the AD7851 as a Read-Only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7851 contains a Control register, ADC output data register, Status register, Test register and 10 Calibration regis-
ters. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibra-
tion registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7851 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register
is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the
data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the overall write reg-
ister hierarchy.
Table I.Write Register Addressing
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register
until the read selection bits are changed in the control register.
Table II.Read Register Addressing
AD7851
CONTROL REGISTER
The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described
below. The power-up status of all bits is 0.
MSB
LSB
Control Register Bit Function Description
52/3 MODE
Table III.Calibration Selection
STATUS REGISTER
The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
START
Figure 6.Flowchart for Reading the Status Register
MSB
LSB
Status Register Bit Function Description
AD7851
CALIBRATION REGISTERS
The AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset and 1 for gain. Data can be written to or read from all
10 calibration registers. In self and system calibration the part automatically modifies the calibration registers; only if the user needs
to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-
dressed (see Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should
not attempt to read from and write to the calibration registers at the same time.
Table IV.Calibration Register Addressing
Writing to/Reading from the Calibration Registers
For writing to the calibration registers a write to the control reg-
ister is required to set the CALSLT0 and CALSLT1 bits. For
reading from the calibration registers a write to the control reg-
ister is required to set the CALSLT0 and CALSLT1 bits, but
also to set the RDSLT1 and RDSLT0 bits to 10 (this addresses
the calibration registers for reading). The calibration register
pointer is reset on writing to the control register setting the
CALSLT1 and CALSLT0 bits, or upon completion of all the
calibration register write/read operations. When reset it points
to the first calibration register in the selected write/read
sequence. The calibration register pointer will point to the gain
calibration register upon reset in all but one case, this case be-
ing where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-
bration register is being accessed, the calibration register
pointer will be automatically incremented after each calibration
register write/read operation. The order in which the 10 calibra-
tion registers are arranged is shown in Figure 7. The user may
abort at any time before all the calibration register write/read
operations are completed, and the next control register write
operation will reset the calibration register pointer. The flow-
chart in Figure 8 shows the sequence for writing to the calibra-
tion registers and Figure 9 for reading.
CALIBRATION REGISTERS
(1)
(2)
(3)
(10)
CALIBRATION REGISTER ADDRESS POINTER POSITION IS
DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS
ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.
Figure 7.Calibration Register Arrangement
When reading from the calibration registers there will always be
two leading zeros for each of the registers. When operating in
serial Interface Mode 1, the read operations to the calibration
registers cannot be aborted. The full number of read operations
must be completed (see section on serial Interface Mode 1 tim-
ing for more detail).
Figure 8.Flowchart for Writing to the Calibration Registers
START
Figure 9.Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration Register
The offset calibration register contains 16 bits, two leading zeros
and 14 data bits. By changing the contents of the offset register,
different amounts of offset on the analog input signal can be
compensated for.Increasing the number in the offset calibration
register compensates for negative offset on the analog input sig-
nal, and decreasing the number in the offset calibration register
compensates for positive offset on the analog input signal. The
default value of the offset calibration register is 0010 0000 0000
0000 approximately. This is not an exact value, but the value in
the offset register should be close to this value. Each of the 14
data bits in the offset register is binary weighted; the MSB has a
weighting of 5% of the reference voltage, the MSB-1 has a
weighting of 2.5%, the MSB-2 has a weighting of 1.25%, and so
on down to the LSB which has a weighting of 0.0006%.
This gives a resolution of ±0.0006% of VREF approximately.
More accurately the resolution is ±(0.05 × VREF)/213 volts =
±0.015 mV, with a 2.5 V reference. The maximum offset that
can be compensated for is ±5% of the reference voltage, which
equates to ±125mV with a 2.5V reference and ±250 mV with a
5 V reference.If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5V, what code needs to be written to the
offset register to compensate for the offset2.5V reference implies that the resolution in the offset reg-
ister is 5% × 2.5 V/213 = 0.015 mV.+20 mV/0.015mV =
1310.72; rounding to the nearest number gives 1311.In
binary terms this is 0101 0001 1111, therefore decrease the
offset register by 0101 0001 1111.
This method of compensating for offset in the analog input sig-
nal allows for fine tuning the offset compensation. If the offset
on the analog input signal is known, there will be no need to
apply the offset voltage to the analog input pins and do a system
calibration. The offset compensation can take place in software.
Adjusting the Gain Calibration Register
The gain calibration register contains 16 bits, two leading 0s
and 14 data bits. The data bits are binary weighted as in the off-
set calibration register. The gain register value is effectively mul-
tiplied by the analog input to scale the conversion result over the
full range.Increasing the gain register compensates for a
smaller analog input range and decreasing the gain register com-
pensates for a larger input range. The maximum analog input
range that the gain register can compensate for is 1.025 times
the reference voltage, and the minimum input range is 0.975
times the reference voltage.
AD7851
CIRCUIT INFORMATION
The AD7851 is a fast, 14-bit single supply A/D converter. The
part requires an external 6/7 MHz master clock (CLKIN), two
CREF capacitors, a CONVST signal to start conversion and
power supply decoupling capacitors. The part provides the user
with track/hold, on-chip reference, calibration features, A/D
converter and serial interface logic functions on a single chip.
The A/D converter section of the AD7851 consists of a conven-
tional successive-approximation converter based around a ca-
pacitor DAC. The AD7851 accepts an analog input range of
0 V to +VDD where the reference can be tied to VDD. The refer-
ence input to the part is buffered onchip.
A major advantage of the AD7851 is that a conversion can be
initiated in software as well as applying a signal to the CONVST
pin. Another innovative feature of the AD7851 is self-calibration
on power-up, which is initiated having a 0.01μF capacitor from
the CAL pin to AGND, to give superior dc accuracy. The part
should be allowed 150 ms after power-up to perform this auto-
matic calibration before any reading or writing takes place. The
part is available in a 24-pin SSOP package and this offers the user
considerable space saving advantages over alternative solutions.
CONVERTER DETAILS
The master clock for the part must be applied to the CLKIN
pin. Conversion is initiated on the AD7851 by pulsing the
CONVST input or by writing to the control register and setting
the CONVST bit to 1. On the rising edge of CONVST (or at
the end of the control register write operation), the on-chip
track/hold goes from track to hold mode. The falling edge of the
CLKIN signal which follows the rising edge of the edge of
CONVST signal initiates the conversion, provided the rising
edge of CONVST occurs at least 10 ns typically before this
CLKIN edge.The conversion cycle will take 18.5 CLKIN peri-
ods from this CLKIN falling edge. If the 10 ns setup time is
ANALOG (5V)
SUPPLY
UNIPOLAR RANGE
SELECTION BITS
0.01µF
INTERNAL
REFERENCE
0V TO VREF
7MHz/6MHz
OSCILLATOR
333kHz/285kHz PULSE
GENERATOR
OPTIONAL
EXTERNAL
REFERENCE
not met, the conversion will take 19.5 CLKIN periods. The
maximum specified conversion time is 3.25 μs (6 MHz ) and
2.8 μs (7 MHz) for the A and K Grades respectively for the
AD7851 (19.5 tCLKIN, CLKIN = 6/7 MHz). When a conversion
is completed, the BUSY output goes low, and then the result of
the conversion can be read by accessing the data through the se-
rial interface. To obtain optimum performance from the part,
the read operation should not occur during the conversion or
500ns prior to the next CONVST rising edge. However, the
maximum throughput rates are achieved by reading/writing dur-
ing conversion, and reading/writing during conversion is likely
to degrade the Signal to (Noise + Distortion) by only 0.5 dBs. The
AD7851 can operate at throughput rates up to 333 kHz. For the
AD7851 a conversion takes 19.5 CLKIN periods, 2 CLKIN
periods are needed for the acquisition time giving a full cycle
time of 3.59 μs (= 279 kHz, CLKIN = 6 MHz) for the K grade
and 3.08 μs (= 325 kHz, CLKIN = 7 MHz) for the A grade.
TYPICAL CONNECTION DIAGRAM
Figure 10 shows a typical connection diagram for the AD7851.
The DIN line is tied to DGND so that no data is written to the
part. The AGND and the DGND pins are connected together
at the device for good noise suppression. The CAL pin has a
0.01 μF capacitor to enable an automatic self-calibration on
power-up. The SCLK and SYNC are configured as outputs by
having SM1 and SM2 at DVDD. The conversion result is output
in a 16-bit word with 2 leading zeros followed by the MSB of
the 14-bit result. Note that after the AVDD and DVDD power-up,
the part will require 150 ms for the internal reference to settle
and for the automatic calibration on power-up to be completed.
For applications where power consumption is a major concern,
the SLEEP pin can be connected to DGND. See Power-Down
section for more detail on low power applications.
ANALOG INPUT
The equivalent circuit of the analog input section is shown in
Figure 11. During the acquisition interval the switches are
both in the track position and the AIN(+) charges the 20 pF
capacitor through the 125 Ω resistance. On the rising edge of
CONVST switches SW1 and SW2 go into the hold position
retaining charge on the 20pF capacitor as a sample of the signal
on AIN(+). The AIN(–) is connected to the 20 pF capacitor,
and this unbalances the voltage at node A at the input of the
comparator. The capacitor DAC adjusts during the remainder of
the conversion cycle to restore the voltage at node A to the cor-
rect value. This action transfers a charge, representing the analog
input signal, to the capacitor DAC which in turn forms a digital
representation of the analog input signal. The voltage on the
AIN(–) pin directly influences the charge transferred to the
capacitor DAC at the hold instant. If this voltage changes during
the conversion period, the DAC representation of the analog
input voltage will be altered. Therefore it is most important that
the voltage on the AIN(–) pin remains constant during the con-
version period. Furthermore, it is recommended that the AIN(–)
pin is always connected to AGND or to a fixed dc voltage.SW1
TRACK
HOLD
125Ω
125Ω
AIN(+)
AIN(–)
CREF2
Figure 11.Analog Input Equivalent Circuit
Acquisition Time
The track and hold amplifier enters its tracking mode on the fall-
ing edge of the BUSY signal. The time required for the track and
hold amplifier to acquire an input signal will depend on how
quickly the 20 pF input capacitance is charged. The acquisition
time is calculated using the formula:
tACQ = 9 × (RIN + 125 Ω) × 20 pF
where RIN is the source impedance of the input signal, and
125Ω, 20 pF is the input R, C.
DC/AC Applications
For dc applications high source impedances are acceptable, pro-
vided there is enough acquisition time between conversions to
charge the 20 pF capacitor. The acquisition time can be calcu-
lated from the above formula for different source impedances.
For example with RIN = 5 kΩ, the required acquisition time will
be 922ns.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the AIN(+) pin, as shown in Figure 13. In applica-
tions where harmonic distortion and signal to noise ratio are
critical, the analog input should be driven from a low impedance
source.Large source impedances will significantly affect the ac
performance of the ADC. This may necessitate the use of an in-
put buffer amplifier. The choice of the op amp will be a function
When no amplifier is used to drive the analog input the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will degrade.
Figure 12 shows a graph of the total harmonic distortion vs.
analog input signal frequency for different source impedances.
With the setup as in Figure 13, the THD is at the –90dB level.
With a source impedance of 1kΩ and no capacitor on the
AIN(+) pin, the THD increases with frequency.
Figure 12.THD vs. Analog Input Frequency
In a single supply application (5 V), the V+ and V– of the op
amp can be taken directly from the supplies to the AD7851
which eliminates the need for extra external power supplies.
When operating with rail-to-rail inputs and outputs at frequen-
cies greater than 10 kHz, care must be taken in selecting the
particular op amp for the application. In particular, for single
supply applications the input amplifiers should be connected in
a gain of –1 arrangement to get the optimum performance. Fig-
ure 13 shows the arrangement for a single supply application
with a 10 Ω and 10 nF low-pass filter (cutoff frequency 320
kHz) on the AIN(+) pin. Note that the 10nF is a capacitor with
good linearity to ensure good ac performance. Recommended
single supply op amp is the AD820.
Figure 13.Analog Input Buffering
AD7851
4.096 V/16384 = 0.25 mV when VREF = 4.096 V. The ideal in-
put/output transfer characteristic for the unipolar range is shown
in Figure 16.
Figure 16.AD7851 Unipolar Transfer Characteristic
Figure 15 shows the AD7851’s ±VREF/2 bipolar analog input
configuration (where AIN(+) cannot go below 0 V so for the full
bipolar range then the AIN(–) pin should be biased to +VREF/2).
Once again the designed code transitions occur midway between
successive integer LSB values. The output coding is 2s comple-
ment with 1 LSB = 16384 = 4.096 V/16384 = 0.25 mV. The
ideal input/output transfer characteristic is shown in
Figure 17.
Figure 17.AD7851 Bipolar Transfer Characteristic
Input Ranges
The analog input range for the AD7851 is 0 V to VREF in both
the unipolar and bipolar ranges.
The only difference between the unipolar range and the bipolar
range is that in the bipolar range the AIN(–) has to be biased up
to +VREF/2 and the output coding is 2s complement (See Table
V and Figures 14 and 15). The unipolar or bipolar mode is se-
lected by the AMODE pin (0 for the unipolar range and 1 for
the bipolar range).
Table V.Analog Input Connections
NOTESOutput code format is straight binary.Range is ±VREF/2 biased about VREF/2. Output code format is 2s complement.
Note that the AIN(–) pin on the AD7851 can be biased up
above AGND in the unipolar mode also, if required. The ad-
vantage of biasing the lower end of the analog input range away
from AGND is that the user does not have to have the analog
input swing all the way down to AGND. This has the advantage
in true single supply applications that the input amplifier does
not have to swing all the way down to AGND. The upper end of
the analog input range is shifted up by the same amount. Care
must be taken so that the bias applied does not shift the upper
end of the analog input above the AVDD supply. In the case
where the reference is the supply, AVDD, the AIN(–) must be
tied to AGND in unipolar mode.UNIPOLAR
ANALOG
INPUT RANGE
SELECTEDSTRAIGHT
BINARY
FORMAT
VIN = 0 TO VREF
Figure 14.0 V to VREF Unipolar Input Configuration
Transfer Functions
For the unipolar range the designed code transitions occur mid-
way between successive integer LSB values (i.e., 1/2 LSB,
3/2LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is
straight binary for the unipolar range with 1 LSB = FS/16384 =
COMPLEMENT
FORMATVREF/2UNIPOLAR
ANALOG
INPUT RANGE
SELECTEDVIN = 0 TO VREF
Figure 15.±VREF/2 about VREF/2 Bipolar Input Configuration
REFERENCE SECTION
For specified performance, it is recommended that when using
an external reference this reference should be between 4 V and
the analog supply AVDD. The connections for the relevant refer-
ence pins are shown in the typical connection diagrams. If the
internal reference is being used, the REFIN/REFOUT pin should
have a 100nF capacitor connected to AGND very close to the
REFIN/REFOUT pin. These connections are shown in Figure 18.
If the internal reference is required for use external to the ADC,
it should be buffered at the REFIN/REFOUT pin and a 100 nF
connected from this pin to AGND. The typical noise performance
for the internal reference, with 5V supplies is 150nV/√Hz @kHz and dc noise is 100 μV p-p.
ANALOG
SUPPLY
+5V
10Ω
Figure 18.Relevant Connections When Using Internal
Reference
The other option is that the REFIN/REFOUT pin be overdriven
by connecting it to an external reference. This is possible due to
the series resistance from the REFIN/REFOUT pin to the internal
reference. This external reference can have a range that includes
AVDD.When using AVDD as the reference source, the 100nF
capacitor from the REFIN/REFOUT pin to AGND should be as
close as possible to the REFIN/REFOUT pin, and also the CREF1
pin should be connected to AVDD to keep this pin at the same
level as the reference.The connections for this arrangement are
shown in Figure 19. When using AVDD it may be necessary to
add a resistor in series with the AVDD supply. This will have the
effect of filtering the noise associated with the AVDD supply.
ANALOG
SUPPLY
+5V
10Ω
10Ω
Figure 19.Relevant Connections When Using AVDD as the
AD7851 PERFORMANCE CURVES
Figure 20 shows a typical FFT plot for the AD7851 at 333 kHz
sample rate and 10 kHz input frequency.
FREQUENCY – kHz
SNR – dB6080
–100
Figure 20.FFT Plot
Figure 21 shows the SNR versus Frequency for 5V supply and
a 4.096 external references (5V reference is typically 1dB bet-
ter performance).
INPUT FREQUENCY – kHz1662050120140
S(N+D) RATIO – dB80100
Figure 21.SNR vs. Frequency
Figure 22 shows the Power Supply Rejection Ratio versus
Frequency for the part. The Power Supply Rejection Ratio is
defined as the ratio of the power in ADC output at frequency f
to the power of a full-scale sine wave.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power of a full-
scale sine wave. Here a 100 mV peak-to-peak sine wave is
coupled onto the AVDD supply while the digital supply is left
unaltered.
AD7851
INPUT FREQUENCY – kHz
PSRR – dB
63.574.887.4
Figure 22.PSRR vs. Frequency
POWER-DOWN OPTIONS
The AD7851 provides flexible power management to allow the
user to achieve the best power performance for a given through-
put rate. The power management options are selected by pro-
gramming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the SLEEP pin. Table VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware or a
combination of both. The AD7851 can be fully or partially pow-
ered down. When fully powered down, all the on-chip circuitry
is powered down and IDD is 1 μA typ. If a partial power-down is
selected, then all the on-chip circuitry except the reference is
powered down and IDD is 400μA typ. The choice of full or par-
tial power-down does not give any significant improvement in
throughput with a power-down between conversions. This is dis-
cussed in the next section—Power-Up Times. But a partial
power-down does allow the on-chip reference to be used exter-
nally even though the rest of the AD7851 circuitry is powered
down. It also allows the AD7851 to be powered up faster after
a long power-down period when using the on-chip reference
(See Power-Up Times—Using On-Chip Reference).
When using the SLEEP pin, the power management bits
PMGT1 and PMGT0 should be set to zero (default status on
power-up). Bringing the SLEEP pin logic high ensures normal
operation, and the part does not power down at any stage. This
may be necessary if the part is being used at high throughput
rates when it is not possible to power down between conver-
sions. If the user wishes to power down between conversions at
lower throughput rates (i.e., <100 kSPS for the AD7851) to
achieve better power performances, then the SLEEP pin should
be tied logic low.
If the power-down options are to be selected in software only,
then the SLEEP pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a Full Power-Down, Full Power-Up, Full Power-
Down Between Conversions, and a Partial Power-Down
Between Conversions can be selected.
A combination of hardware and software selection can also be
used to achieve the desired effect.
Table VI.Power Management Options
NOTE
SW = Software selection, HW = Hardware selection.
0V TO VREF
INPUT
CURRENT, I = 12mA TYP
ANALOG
(+5V)
SUPPLY
INTERNAL
REFERENCE
6/7MHz
OSCILLATOR
285/333kHz PULSE
GENERATOR

Partno	Mfg	Dc	Qty	Available	Descript
AD7851AN		N/a	18	avai	14-Bit 333 kSPS Serial A/D Converter
AD7851AN	ADI	N/a	50	avai	14-Bit 333 kSPS Serial A/D Converter
AD7851AR	AD	N/a	16	avai	14-Bit 333 kSPS Serial A/D Converter
AD7851ARS	AD	N/a	20	avai	14-Bit 333 kSPS Serial A/D Converter
AD7851KN	AD	N/a	200	avai	14-Bit 333 kSPS Serial A/D Converter
AD7851KR	AD	N/a	105	avai	14-Bit 333 kSPS Serial A/D Converter