AD7846BP ,LC2MOS 16-Bit Voltage Output DACCHARACTERISTICSOutput Voltage Swing V + 4 to V + 4 to V maxSS SSV – 3 V – 3DD DDResistive Load 2 2 ..
AD7846BP ,LC2MOS 16-Bit Voltage Output DACspecifications T to T , unless otherwise noted.)MIN MAXParameter J, A Versions K, B Versions Unit T ..
AD7846BPZ , LC2MOS 16-Bit Voltage Output DAC
AD7846JN ,LC2MOS 16-Bit Voltage Output DACCHARACTERISTICSto –15.75 V; V = +4.75 V to +5.25 V; R connected to 0 V.)CC INLimit atT to TMIN MAXP ..
AD7846JP ,LC2MOS 16-Bit Voltage Output DACCHARACTERISTICSto –15.75 V; V = +4.75 V to +5.25 V; R connected to 0 V.)CC INLimit atT to TMIN MAXP ..
AD7846JP-REEL ,16-Bit Voltage Output CMOS DACCHARACTERISTICSOutput Voltage Swing V + 4 to V + 4 to V maxSS SSV – 3 V – 3DD DDResistive Load 2 2 ..
ADM232LJRZ , 5 V-Powered CMOS RS-232 Drivers/Receivers
ADM233LAN ,+5 V Powered CMOS RS-232 Drivers/Receivers+5 V PoweredaCMOS RS-232 Drivers/ReceiversADM223/ADM230L–ADM241LADM232L TYPICAL OPERATING CIRCUIT
ADM233LJN ,+5 V Powered CMOS RS-232 Drivers/Receiversapplications where ±12 V is not available. The ADM223, These converters convert the +5 V input pow ..
ADM234LAN ,+5 V Powered CMOS RS-232 Drivers/ReceiversFEATURESSingle 5 V Power Supply+5V INPUTMeets All EIA-232-E and V.28
ADM234LAR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*Thermal Impedance, θJA(T = ..
ADM234LJN ,+5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION All members of the ADM230L family, except the ADM231LThe ADM2xx family of line ..
AD7846AP-AD7846AQ-AD7846BP-AD7846JN-AD7846JP-AD7846KN-AD7846KP
LC2MOS 16-Bit Voltage Output DAC
REV.E
LC2MOS
16-Bit Voltage Output DAC
FEATURES
16-Bit Monotonicity over Temperature�2 LSBs Integral Linearity Error
Microprocessor Compatible with Readback Capability
Unipolar or Bipolar Output
Multiplying Capability
Low Power (100 mW Typical)
GENERAL DESCRIPTIONThe AD7846 is a 16-bit DAC constructed with Analog Devices’2MOS process. It has VREF+ and VREF– reference inputs and
an on-chip output amplifier. These can be configured to give a
unipolar output range (0 V to +5 V, 0 V to +10 V) or bipolar
output ranges (±5 V, ±10 V).
The DAC uses a segmented architecture. The 4 MSBs in the
DAC latch select one of the segments in a 16-resistor string.
Both taps of the segment are buffered by amplifiers and fed to a
12-bit DAC, which provides a further 12 bits of resolution. This
architecture ensures 16-bit monotonicity. Excellent integral
linearity results from tight matching between the input offset
voltages of the two buffer amplifiers.
In addition to the excellent accuracy specifications, the AD7846
also offers a comprehensive microprocessor interface. There are
16 data I/O pins, plus control lines (CS, R/W, LDAC and CLR).
R/W and CS allow writing to and reading from the I/O latch.
This is the readback function which is useful in ATE applica-
tions. LDAC allows simultaneous updating of DACs in a multi-
DAC system and the CLR line will reset the contents of the
DAC latch to 00 . . . 000 or 10 . . . 000 depending on the state
of R/W. This means that the DAC output can be reset to 0V in
both the unipolar and bipolar configurations.
The AD7846 is available in 28-lead plastic, ceramic, and PLCC
packages.
FUNCTIONAL BLOCK DIAGRAM
VREF –
VREF +
VSSDGND
CLR
LDAC
R/W
VOUT
RIN
VDDVCC
DB15DB0
PRODUCT HIGHLIGHTS16-Bit Monotonicity
The guaranteed 16-bit monotonicity over temperature makes
the AD7846 ideal for closed-loop applications.Readback
The ability to read back the DAC register contents minimizes
software routines when the AD7846 is used in ATE systems.Power Dissipation
Power dissipation of 100 mW makes the AD7846 the lowest
power, high accuracy DAC on the market.
OUTPUT CHARACTERISTICS
DIGITAL OUTPUTS
POWER REQUIREMENTS
NOTESTemperature ranges as follows: J, K Versions: 0°C to +70°C; A, B Versions: –40°C to +85°CGuaranteed by design and characterization, not production tested.The AD7846 is functional with power supplies of ±12 V. See Typical Performance Curves.Sensitivity of Gain Error, Offset Error and Bipolar Zero Error to VDD, VSS variations.
Specifications subject to change without notice.
AD7846–SPECIFICATIONS1
(VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V.
VOUT loaded with 2 k�, 1000 pF to 0 V; VREF+ = +5 V; RIN connected to 0 V. All
specifications TMIN to TMAX, unless otherwise noted.)
t10
t11
NOTESTiming specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed
from a voltage level of 1.6 V.t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
AD7846AC Feedthrough
Output Noise Voltage
Density 1 kHz–100 kHz
NOTESLDAC = 0. Settling time does not include deglitching time of 2.5 µs (typ).
Specifications subject to change without notice.
TIMING CHARACTERISTICS(VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V)High Z to VOLa.High Z to VOH
Figure 1.Load Circuits for Access Time (t6)
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are not
subjecttotest.(VREF+= +5V; VDD=+14.25Vto+15.75V;VSS=–14.25V–15.75V;VCC=+4.75Vto+5.25V;RINconnectedto0V.)
AD7846
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS1VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.4 V to +17 V
VCC to DGND . . . . . . . . . . . . . . .–0.4 V, VDD + 0.4 V or +7 V
(Whichever Is Lower)
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.4 V to –17 V
VREF+ to DGND . . . . . . . . . . . . . . . .VDD + 0.4 V, VSS – 0.4 V
VREF– to DGND . . . . . . . . . . . . . . . .VDD + 0.4 V, VSS – 0.4 V
VOUT to DGND2 . . . . . . . .VDD + 0.4 V, VSS – 0.4 V or ±10 V
(Whichever Is Lower)
RIN to DGND . . . . . . . . . . . . . . . . . .VDD + 0.4 V, VSS – 0.4 V
Digital Input Voltage to DGND . . . . . .–0.4 V to VCC + 0.4 V
Digital Output Voltage to DGND . . . . .–0.4 V to VCC + 0.4 V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Operating Temperature Range
J, K Versions . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering) . . . . . . . . . . . . . . . . . .+300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
2VOUT may be shorted to DGND, VDD, VSS, VCC provided that the power dissipation
of the package is not exceeded.
CAUTIONESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
TERMINOLOGY
LEAST SIGNIFICANT BITThis is the analog weighting of 1 bit of the digital word in a DAC.
For the AD7846, 1 LSB = (VREF+–VREF–)/216.
Relative AccuracyRelative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after adjust-
ing for both endpoints (i.e., offset and gain errors are adjusted
out) and is normally expressed in least significant bits or as a
percentage of full-scale range.
Differential NonlinearityDifferential nonlinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of ±1 LSB over the operating
temperature range ensures monotonicity.
Gain Error
Offset ErrorThis is the error present at the device output with all 0s loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.
Bipolar Zero ErrorWhen the AD7846 is connected for bipolar output and 10...000
is loaded to the DAC, the deviation of the analog output from the
ideal midscale of 0 V is called the bipolar zero error.
Digital-to-Analog Glitch ImpulseThis is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or a
voltage.
Multiplying Feedthrough ErrorThis is an ac error due to capacitive feedthrough from either of
the VREF terminals to VOUT when the DAC is loaded with all 0s.
PIN FUNCTION DESCRIPTION
Table I.Output Voltage Ranges
PIN CONFIGURATIONS
DIP
PLCC
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
LDAC
CLR
R/W
DGND
DB6
VOUT
RIN
VREF+
VREF–
VSS
DB15
DB14
DB0DB1DB2DB3DB4DB5
DB13DB12DB11DB10
DB9DB8DB7
AD7846
VCC
AD7846–Typical Performance CurvesFigure 6.Large Signal Frequency
Response
Figure 9.Digital-to-Analog Glitch
Impulse With Internal Deglitcher
(10 . . . 000 to 011 . . . 111 Transition)
Figure 12. Spectral Response of
Digitally Constructed Sine Wave
Figure 5.AC Feedthrough vs.
Frequency
Figure 8.Digital-to-Analog Glitch
Impulse Without Internal Deglitcher
(10 . . . 000 to 011 . . . 111 Transition)
Figure 11.Pulse Response
(Small Signal)
Figure 4.AC Feedthrough. VREF+ =
1 V rms, 10 kHz Sine Wave
Figure 7.Noise Spectral Density
Figure 10.Pulse Response
(Large Signal)
Figure 13.Typical Linearity vs. VDD/VSS
Figure 14.Typical Monotonicity vs.
VDD/VSS
CIRCUIT DESCRIPTION
Digital SectionFigure 15 shows the digital control logic and on-chip data
latches in the AD7846. Table II is the associated truth table.
The D/A converter has two latches that are controlled by four
signals: CS, R/W, LDAC and CLR. The input latch is con-
nected to the data bus (DB15–DB0). A word is written to the
input latch by bringing CS low and R/W low. The contents of
the input latch may be read back by bringing CS low and R/W
high. This feature is called “readback” and is used in system
diagnostic and calibration routines.
Data is transferred from the input latch to the DAC latch with
the LDAC strobe. The equivalent analog value of the DAC
latch contents appears at the DAC output. The CLR pin resets
the DAC latch contents to 000 . . . 000 or 100 . . . 000, depend-
ing on the state of R/W. Writing a CLR loads 000 . . . 000 and
reading a CLR loads 100 . . . 000. To reset a DAC to 0 V in a
unipolar system the user should exercise CLR while R/W is low;
to reset to 0V in a bipolar system exercise the CLR while R/W
is high.
Figure 15.Input Control Logic
Table II.Control Logic Truth Table
D/A ConversionFigure 16 shows the D/A section of the AD7846. There are
three DACs, each of which have their own buffer amplifiers.
DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor
string but have their own analog multiplexers. The voltage refer-
ence is applied to the resistor string. DAC3 is a 12-bit voltage
mode DAC with its own output stage.
The 4 MSBs of the 16-bit digital code drive DAC1 and DAC2
while the 12 LSBs control DAC3. Using DAC1 and DAC2, the
MSBs select a pair of adjacent nodes on the resistor string and
present that voltage to the positive and negative inputs of
DAC3. This DAC interpolates between these two voltages to
produce the analog output voltage.
To prevent nonmonotonicity in the DAC due to amplifier offset
voltages, DAC1 and DAC2 “leap-frog” along the resistor string.
For example, when switching from Segment 1 to Segment 2,
DAC1 switches from the bottom of Segment 1 to the top of
Segment 2 while DAC2 stays connected to the top of Segment
1. The code driving DAC3 is automatically complemented to
compensate for the inversion of its inputs. This means that any
linearity effects due to amplifier offset voltages remain un-
changed when switching from one segment to the next and
AD7846Figure 16.D/A Conversion
Output StageThe output stage of the AD7846 is shown in Figure 17. It is
capable of driving a 2 kΩ/1000 pF load. It also has a resistor
feedback network which allows the user to configure it for gains
of one or two. Table I shows the different output ranges that are
possible.
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5µs
after the leading edge of LDAC. This short state keeps the DAC
output at its previous voltage while the AD7846 is internally
changing to its new value. So, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC is tied permanently low, the deglitching will not be in
operation. Figures 8 and 9 show the outputs of the AD7846
without and with the deglitcher.
Figure 17.Output Stage
UNIPOLAR BINARY OPERATIONFigure 18 shows the AD7846 in the unipolar binary circuit
configuration. The DAC is driven by the AD586, +5 V refer-
ence. Since RIN is tied to 0 V, the output amplifier has a gain of
2 and the output range is 0V to +10 V. If a 0V to +5 V range is
required, RIN should be tied to VOUT, configuring the output
stage for a gain of 1. Table III gives the code table for the circuit
of Figure 18.
+15V+5VC1
1�F
SIGNAL
GROUND
–15V*ADDITIONAL PINS
OMITTED FOR CLARITY
VOUT
(0V TO +10V)Figure 18.Unipolar Binary Operation
Table III.Code Table for Figure 18NOTE
1 LSB = 10 V/216 = 10 V/65536 = 152 µV.
Offset and gain may be adjusted in Figure 18 as follows: To
adjust offset, disconnect the VREF– input from 0 V, load the
DAC with all 0s and adjust the VREF– voltage until VOUT = 0 V.
For gain adjustment, the AD7846 should be loaded with all 1s
and R1 adjusted until VOUT = 10 (65535)/(65536) = 9.999847 V.
If a simple resistor divider is used to vary the VREF– voltage, it is
important that the temperature coefficients of these resistors
match that of the DAC input resistance (–300 ppm/°C). Other-
wise, extra offset errors will be introduced over temperature.
Many circuits will not require these offset and gain adjustments.
