AD7845KP ,LC2MOS Complete 12-Bit Multiplying DACspecifications include amplifier performance.The 12 data inputs drive latches which are controlled ..
AD7845KR ,LC2MOS Complete 12-Bit Multiplying DACCHARACTERISTICS (V = +15 V, 6 5%. V = –15 V, 6 5%. V = +10 V. AGND = DGND = O V.)DD SS REFLimit at ..
AD7845SQ , LC2MOS Complete 12-Bit Multiplying DAC
AD7846AP ,LC2MOS 16-Bit Voltage Output DACFEATURESFUNCTIONAL BLOCK DIAGRAM16-Bit Monotonicity over TemperatureV V2 LSBs Integral Linearity E ..
AD7846AQ ,LC2MOS 16-Bit Voltage Output DACGENERAL DESCRIPTIONPRODUCT HIGHLIGHTSThe AD7846 is a 16-bit DAC constructed with Analog Devices’1. ..
AD7846BD ,16-Bit Voltage Output CMOS DACspecifications T to T , unless otherwise noted.)MIN MAXParameter J, A Versions K, B Versions Unit T ..
ADM232LJN ,+5 V Powered CMOS RS-232 Drivers/ReceiversSPECIFICATIONS32L, 34L, 36L, 38L, 39L, 41L);V = +5 V 6 5% (ADM230L, 33L, 35L, 37L); V+ = 7.5 V to 1 ..
ADM232LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*Thermal Impedance, θJA(T = ..
ADM232LJRZ , 5 V-Powered CMOS RS-232 Drivers/Receivers
ADM233LAN ,+5 V Powered CMOS RS-232 Drivers/Receivers+5 V PoweredaCMOS RS-232 Drivers/ReceiversADM223/ADM230L–ADM241LADM232L TYPICAL OPERATING CIRCUIT
ADM233LJN ,+5 V Powered CMOS RS-232 Drivers/Receiversapplications where ±12 V is not available. The ADM223, These converters convert the +5 V input pow ..
ADM234LAN ,+5 V Powered CMOS RS-232 Drivers/ReceiversFEATURESSingle 5 V Power Supply+5V INPUTMeets All EIA-232-E and V.28
AD7845AQ-AD7845JN-AD7845JP-AD7845JR-AD7845KN-AD7845KP-AD7845KR
LC2MOS Complete 12-Bit Multiplying DAC
REV.B
LC2MOS
Complete 12-Bit Multiplying DAC
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTSVoltage Output Multiplying DAC
The AD7845 is the first DAC which has a full 4-quadrant
multiplying capability and an output amplifier on chip. All
specifications include amplifier performance.Matched Application Resistors
Three application resistors provide an easy facility for gain
ranging, voltage offsetting, etc.Space Saving
The AD7845 saves space in two ways. The integration of the
output amplifier on chip means that chip count is reduced.
The part is housed in skinny 24-lead 0.3" DIP, 28-terminal
LCC and PLCC and 24-terminal SOIC packages.
GENERAL DESCRIPTIONThe AD7845 is the industry’s first 4-quadrant multiplying D/A
converter with an on-chip amplifier. It is fabricated on the2MOS process, which allows precision linear components
and digital circuitry to be implemented on the same chip.
The 12 data inputs drive latches which are controlled by stan-
dard CS and WR signals, making microprocessor interfacing
simple. For stand-alone operation, the CS and WR inputs can
be tied to ground, making all latches transparent. All digital
inputs are TTL and 5 V CMOS compatible.
The output amplifier can supply –10 V into a 2 kW load. It is
internally compensated, and its input offset voltage is low due to
laser trimming at wafer level. For normal operation, RFB is tied
to VOUT, but the user may alternatively choose RA, RB or RC to
scale the output voltage range.
FEATURES
12-Bit CMOS MDAC with Output Amplifier
4-Quadrant Multiplication
Guaranteed Monotonic (TMIN to TMAX)
Space-Saving 0.3" DIPs and 24- or 28-Terminal Surface
Mount Packages
Application Resistors On Chip for Gain Ranging, etc.
Low Power LC2MOS
APPLICATIONS
Automatic Test Equipment
Digital Attenuators
Programmable Power Supplies
Programmable Gain Amplifiers
Digital-to-4–20 mA Converters
(VDD = +15 V, 6 5%, VSS = –15 V, 6 5%, VREF = +10 V, AGND = DGND = O V,
VOUT connected to RFB. VOUT load = 2 kV, 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
AD7845–SPECIFICATIONS1APPLICATION RESISTOR
POWER SUPPLY
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance and are not subject to test.OUTPUT CHARACTERISTICS
tCH
tWR
tDS
NOTESGuaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1(VDD = +15 V, 6 5%. VSS = –15 V, 6 5%. VREF = +10 V. AGND = DGND = O V.)
ORDERING GUIDE1NOTESAnalog Devices reserves the right to ship either ceramic (D-24A) or cerdip
(Q-24) hermetic packages.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7845 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . .0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . .–40°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . .+300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect device
reliability. Only one Absolute Maximum Rating may be applied at any one time.VOUT may be shorted to AGND provided that the power dissipation of the
package is not exceeded.
Figure 1.AD7845 Timing Diagram
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise stated)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17 V
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V
VREF to AGND . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VRFB to AGND . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VRA to AGND . . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VRB to AGND . . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VRC to AGND . . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
Digital Input Voltage to DGND . . . . .–0.3 V to VDD + 0.3 V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . .10 mW/°C
AD7845
PIN CONFIGURATIONS
LCCPLCCDIP, SOIC
DIGITAL-TO-ANALOG GLITCH IMPULSEThis is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is nor-
mally specified as the area of the glitch in either pA-secs or
nV-secs depending upon whether the glitch is measured as a
current or voltage. The measurement takes place with VREF =
AGND.
DIGITAL FEEDTHROUGHWhen the DAC is not selected (i.e., CS is high) high frequency
logic activity on the device digital inputs is capacitively coupled
through the device to show up as noise on the VOUT pin. This
noise is digital feedthrough.
MULTIPLYING FEEDTHROUGH ERRORThis is ac error due to capacitive feedthrough from the VREF
terminal to VOUT when the DAC is loaded with all 0s.
OPEN-LOOP GAINOpen-loop gain is defined as the ratio of a change of output
voltage to the voltage applied at the VREF pin with all 1s loaded
in the DAC. It is specified at dc.
UNITY GAIN SMALL SIGNAL BANDWIDTHThis is the frequency at which the magnitude of the small signal
voltage gain of the output amplifier is 3 dB below unity. The
device is operated as a closed-loop unity gain inverter (i.e.,
DAC is loaded with all 1s).
OUTPUT RESISTANCEThis is the effective output source resistance.
FULL POWER BANDWIDTHFull power bandwidth is specified as the maximum frequency, at
TERMINOLOGY
LEAST SIGNIFICANT BITThis is the analog weighting of 1 bit of the digital word in a
DAC. For the AD7845, 1 LSB =
RELATIVE ACCURACYRelative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for both endpoints (i.e., offset and gain error are ad-
justed out) and is normally expressed in least significant bits or
as a percentage of full-scale range.
DIFFERENTIAL NONLINEARITYDifferential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of +1 LSB max over
the operating temperature range ensures monotonicity.
GAIN ERRORGain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer. See Figure 13.
ZERO CODE OFFSET ERRORThis is the error present at the device output with all 0s loaded
in the DAC. It is due to the op amp input offset voltage and
bias current and the DAC leakage current.
TOTAL HARMONIC DISTORTIONThis is the ratio of the root-mean-square (rms) sum of the har-
monics to the fundamental, expressed in dBs.
Figure 3.Output Voltage Swing vs.
Resistive Load
Figure 6.Typical AD7845 Linearity
vs. Power Supply
Figure 9.Unity Gain Inverter Pulse
Response (Small Signal)
Figure 4.Noise Spectral Density
Figure 7.Multiplying Feedthrough
Error vs. Frequency
Figure 10.Digital-to-Analog Glitch
Impulse (All 1s to All 0s Transition)
Figure 2.Frequency Response, G = –1
Figure 5.THD vs. Frequency
Figure 8.Unity Gain Inverter Pulse
Response (Large Signal)
AD7845
PIN FUNCTION DESCRIPTION (DIP)
CIRCUIT INFORMATION
Digital SectionFigure 11 is a simplified circuit diagram of the AD7845 input
control logic. When CS and WR are both low, the DAC latch is
loaded with the data on the data inputs. All the digital inputs
are TTL, HCMOS and +5 V CMOS compatible, facilitating
easy microprocessor interfacing. All digital inputs incorporate
standard protection circuitry.
Figure 11.AD7845 Input Control Logic
D/A SectionFigure 12 shows a simplified circuit diagram for the AD7845
D/A section and output amplifier.
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A-C. The
remaining 10 bits drive the switches (S0–S9) in a standard R-2R
ladder configuration.
Figure 12.Simplified Circuit Diagram for the AD7845 D/A
Section
Each of the switches A–C steers 1/4 of the total reference cur-
rent with the remaining 1/4 passing through the R-2R section.
An output amplifier and feedback resistor perform the current-
to-voltage conversion giving
VOUT = – D · VREF
where D is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)
The amplifier can maintain –10 V across a 2 kW load. It is inter-
nally compensated and settles to 0.01% FSR (1/2 LSB) in less
than 5 ms. The input offset voltage is laser trimmed at wafer
level. The amplifier slew rate is typically 11 V/ms, and the unity
gain small signal bandwidth is 600 kHz. There are three extra
on-chip resistors (RA, RB, RC) connected to the amplifier invert-
ing terminal. These are useful in a number of applications in-
cluding offset adjustment and gain ranging.
