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AD7843ARQ-AD7843ARQ-REEL7-AD7843ARU
Touch Screen Digitizer
REV.0
ouch Screen Digitizer
FUNCTIONAL BLOCK DIAGRAM
DCLK
GND
+VCC
BUSY
PENIRQDOUTDIN
+VCC
IN3
VREF
IN4
GENERAL DESCRIPTIONThe AD7843 is a 12-bit successive-approximation ADC with a
synchronous serial interface and low on resistance switches for
driving touch screens. The part operates from a single 2.2 V to
5.25 V power supply and features throughput rates greater than
125 kSPS.
The external reference applied to the AD7843 can be varied
from 1 V to +VCC, while the analog input range is from 0 V to
VREF. The device includes a shutdown mode that reduces the
current consumption to less than 1 µA.
The AD7843 features on-board switches. This coupled with low
power and high-speed operation make this device ideal for
battery-powered systems such as personal digital assistants with
resistive touch screens and other portable equipment. The part
is available in a 16-lead 0.15" Quarter Size Outline (QSOP) pack-
age and a 16-lead Thin Shrink Small Outline (TSSOP) package.
FEATURES
4-Wire Touch Screen Interface
Specified Throughput Rate of 125 kSPS
Low Power Consumption:
1.37 mW Max at 125 kSPS with VCC = 3.6 V
Single Supply, VCC of 2.2V to 5.25 V
Ratiometric Conversion
High-Speed Serial Interface
Programmable 8- or 12-Bit Resolution
Two Auxiliary Analog Inputs
Shutdown Mode: 1 �A max
16-Lead QSOP and TSSOP Packages
APPLICATIONS
Personal Digital Assistants
Smart Hand-Held Devices
Touch Screen Monitors
Point-of-Sales Terminals
Pagers
PRODUCT HIGHLIGHTSRatiometric conversion mode available eliminating errors
due to on-board switch resistances.Maximum current consumption of 380 µA while operating at
125 kSPS.Power-down options available.Analog input range from 0 V to VREF.Versatile serial I/O port.
AD7843–SPECIFICATIONS
(VCC = 2.7 V to 3.6 V, VREF = 2.5 V, fSCLK = 2 MHz unless otherwise noted; TA =
–40�C to +85�C, unless otherwise noted.)NOTESTemperature range as follows: A Version: –40°C to +85°C.See Terminology.Guaranteed by design.
tACQ
t10
t11
NOTESSample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.Mark/Space ratio for the SCLK input is 40/60 to 60/40.Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 2.0 V.t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1(TA = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 3.6 V, VREF = 2.5 V)Figure 1.Load Circuit for Digital Output Timing Specifications
AD7843
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7843 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C unless otherwise noted)
+VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Analog Input Voltage to GND . . . . . . .–0.3 V to VCC + 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VCC + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VCC + 0.3 V
VREF to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . .±10 mA
Operating Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
QSOP, TSSOP Package, Power Dissipation . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . .149.97°C/W (QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150.4°C/W (TSSOP)
θJC Thermal Impedance . . . . . . . . . . . . .38.8°C/W (QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27.6°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
NOTESStresses above those listed under Absolute Maximum Rating may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDEAD7843ARQ-REEL
AD7843ARQ-REEL7
AD7843ARU
NOTESLinearity error here refers to integral linearity error.RQ = 0.15" Quarter Size Outline Package.This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes.This EVALUATION BOARD CONTROLLER is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the
CB designators.
PIN CONFIGURATION QSOP/TSSOP
PIN FUNCTION DESCRIPTIONS
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset ErrorThis is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain ErrorThis is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the offset
error has been adjusted out.
Track/Hold Acquisition TimeThe track/hold amplifier enters the acquisition phase on the fifth
falling edge of DCLK after the START bit has been detected.
Three DCLK cycles are allowed for the Track/Hold acquisition
time and the input signal will be fully acquired to the 12-bit
level within this time even with the maximum specified DCLK
frequency. See Analog Input section for more details.
On-ResistanceThis is a measure of the ohmic resistance between the drain and
source of the switch drivers.
TPC 1.Supply Current vs. Temperature
TPC 2.Supply Current vs. +VCC
TPC 3.Change in Gain vs. Temperature
TEMPERATURE – �C
SUPPLY CURRENT
nA
139TPC 4.Power-Down Supply Current vs. Temperature
TPC 5.Maximum Sample Rate vs. +VCC
TPC 6.Change in Offset vs. Temperature
AD7843–Typical Performance Characteristics
SAMPLE RATE – kHz
REFERENCE CURRENT
100TPC 7.Reference Current vs. Sample Rate
+VCC –V
5.0TPC 8.Switch-On-Resistance vs. +VCC (X+, Y+: +VCC to
Pin; X–, Y–: Pin to GND)
SAMPLING RATE – kSPS
ERROR
LSB
1.8TPC 9.Maximum Sampling Rate vs. RIN
TPC 10.Reference Current vs. Temperature
TEMPERATURE – �C
10040200–20–40TPC 11.Switch-On-Resistance vs. Temperature (X+, Y+:
+VCC to Pin; X–, Y–: Pin to GND)
FREQUENCY – kHz
SNR
dB
37.5TPC 12.Auxiliary Channel Dynamic Performance
AD7843
CIRCUIT INFORMATIONThe AD7843 is a fast, low-power, 12-bit, single supply, A/D
converter. The AD7843 can be operated from a 2.2 V to 5.25 V
supply. When operated from either a 5 V supply or a 3 V supply,
the AD7843 is capable of throughput rates of 125 kSPS when
provided with a 2 MHz clock.
The AD7843 provides the user with an on-chip track/hold,
multiplexer, A/D converter, and serial interface housed in a tiny
16-lead QSOP or TSSOP package, which offers the user consid-
erable space-saving advantages over alternative solutions. The
serial clock input (DCLK) accesses data from the part but also
provides the clock source for the successive-approximation A/D
converter. The analog input range is 0 V to VREF (where the
externally-applied VREF can be between 1 V and VCC).
The analog input to the ADC is provided via an on-chip multi-
plexer. This analog input may be any one of the X and Y panel
coordinates. The multiplexer is configured with low resistance
switches that allow an unselected ADC input channel to provide
power and an accompanying pin to provide ground for an exter-
nal device. For some measurements the on-resistance of the
switches may present a source of error. However, with a dif-
ferential input to the converter and a differential reference
architecture this error can be negated.
ADC TRANSFER FUNCTIONThe output coding of the AD7843 is straight binary. The
designed code transitions occur at successive integer LSB values
(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/4096. The ideal
transfer characteristic for the AD7843 is shown in Figure 2 below.
ADC CODE
ANALOG INPUT
1LSB+VREF–1LSBFigure 2.AD7843 Transfer Characteristic
TYPICAL CONNECTION DIAGRAMFigure 3 shows a typical connection diagram for the AD7843 in
a touch screen control application. The AD7843 requires an exter-
nal reference and an external clock. The external reference can
be any voltage between 1 V and VCC. The value of the reference
voltage will set the input range of the converter. The conversion
result is output MSB first followed by the remaining eleven bits
and three trailing zeroes depending on the number of clocks used
per conversion, see the Serial Interface section. For applications
where power consumption is of concern, the power management
option should be used to improve power performance. See
Table III for the available power management options.
TPC 12 shows a typical FFT plot for the auxiliary channels of
the AD7843 at 125 kHz sample rate and 15 kHz input frequency.
TPC 13 shows the power supply rejection ratio versus VCC
supply frequency for the AD7843. The power supply rejection
ratio is defined as the ratio of the power in the ADC output at
full-scale frequency f, to the power of a 100 mV sine wave applied
to the ADC VCC supply of frequency fS:
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power at fre-
quency fS coupled onto the ADC VCC supply. Here a 100 mV
peak-to-peak sine wave is coupled onto the VCC supply. Decou-
pling capacitors of 10 µF and 0.1 µF were used on the supply.
VCC RIPPLE FREQUENCY – kHz
PSRR
dB
–40507090TPC 13.AC PSRR vs. Supply Ripple Frequency
