AD7840 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7840 ,Complete 14-Bit CMOS DACSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDEV to AGND . ..
AD7840AQ ,LC2MOS Complete 14-Bit DACspecifications in bold print are 100% production tested. All other times are sample tested at +25°C ..
AD7840ARS ,LC2MOS Complete 14-Bit DACspecifications, the AD7840 isLDAC signal. A fast data setup time of 21 ns allows direct specified f ..
AD7840JN ,LC2MOS Complete 14-Bit DACspecifications T to T unless othewise noted.)L MIN MAX1 1 1Parameter J, A K, B S Units Test Conditi ..
AD7840JP ,LC2MOS Complete 14-Bit DACCHARACTERISTICSVoltage Output Settling Time Settling Time to within ±1/2 LSB of Final ValuePositive ..
AD7840JP ,LC2MOS Complete 14-Bit DACSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDEV to AGND . ..
ADM232AAN ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTIONEN (ADM242)ADM2xxThe ADM222, ADM232A, ADM242 are a family of high speedSHDN (ADM ..
ADM232AANZ , High-Speed, 5 V, 0.1 F CMOS RS-232 Drivers/Receivers
ADM232AARN ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversSpecificationsTwo Drivers and Two Receivers 0.1µFVCCC1+On-Board DC-DC Converters+5V TO +10V0.1µFV+V ..
ADM232AARNZ-REEL , High-Speed, 5 V, 0.1 F CMOS RS-232 Drivers/Receivers
ADM232AARW ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversSpecificationsTwo Drivers and Two Receivers 0.1µFVCCC1+On-Board DC-DC Converters+5V TO +10V0.1µFV+V ..
ADM232AARWZ-REEL , High-Speed, 5 V, 0.1 F CMOS RS-232 Drivers/Receivers

AD7840
Complete 14-Bit CMOS DAC
REV.BLC2MOS
Complete 14-Bit DAC
FUNCTIONAL BLOCK DIAGRAMFEATURES
Complete 14-Bit Voltage Output DAC
Parallel and Serial Interface Capability
80 dB Signal-to-Noise Ratio
Interfaces to High Speed DSP Processors
e.g., ADSP-2100, TMS32010, TMS32020
45 ns min WR Pulse Width
Low Power – 70 mW typ.
Operates from 65 V Supplies
GENERAL DESCRIPTION
The AD7840 is a fast, complete 14-bit voltage output D/A con-
verter. It consists of a 14-bit DAC, 3 V buried Zener reference,
DAC output amplifier and high speed control logic.
The part features double-buffered interface logic with a 14-bit
input latch and 14-bit DAC latch. Data is loaded to the input
latch in either of two modes, parallel or serial. This data is then
transferred to the DAC latch under control of an asynchronous
LDAC signal. A fast data setup time of 21 ns allows direct
parallel interfacing to digital signal processors and high speed
16-bit microprocessors. In the serial mode, the maximum serial
data clock rate can be as high as 6 MHz.
The analog output from the AD7840 provides a bipolar output
range of ±3 V. The AD7840 is fully specified for dynamic per-
formance parameters such as signal-to-noise ratio and harmonic
distortion as well as for traditional dc specifications. Full power
output signals up to 20 kHz can be created.
The AD7840 is fabricated in linear compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
The part is available in a 24-pin plastic and hermetic
dual-in-line package (DIP) and is also packaged in a 28-termi-
nal plastic leaded chip carrier (PLCC).
PRODUCT HIGHLIGHTS
1. Complete 14-Bit D/A Function
The AD7840 provides the complete function for creating ac
signals and dc voltages to 14-bit accuracy. The part features
an on-chip reference, an output buffer amplifier and 14-bit
D/A converter.
2. Dynamic Specifications for DSP Users
In addition to traditional dc specifications, the AD7840 is
specified for ac parameters including signal-to-noise ratio and
harmonic distortion. These parameters along with important
timing parameters are tested on every device.
3. Fast, Versatile Microprocessor Interface
The AD7840 is capable of 14-bit parallel and serial interfac-
ing. In the parallel mode, data setup times of 21 ns and write
pulse widths of 45 ns make the AD7840 compatible with
modern 16-bit microprocessors and digital signal processors.
In the serial mode, the part features a high data transfer rate
of 6 MHz.
AD7840–SPECIFICATIONS
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = O V, REF IN = +3 V, RL = 2 kV,
CL = 100 pF. All specifications TMIN to TMAX unless othewise noted.)
NOTES
1Temperature ranges are as follows: J, K Versions, 0°C to +70°C; A, B Versions, –25°C to +85°C; S Version, –55°C to +125°C.
2VOUT (pk-pk) = ±3 V
3SNR calculation includes distortion and noise components.
4Using external sample-and-hold (see Testing the AD7840).
5Measured with respect to REF IN and includes bipolar offset error.
6For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
ORDERING GUIDE
NOTESTo order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for military data sheet and availability.N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.This grade will be available to /883B processing only.
TIMING CHARACTERISTICS1, 2
t10
NOTESTiming specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 6 and 8.SCLK mark/space ratio is 40/60 to 60/40.
Specifications subject to change without notice.
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V.)
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS to VDD
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . .0 V to VDD
REF IN to AGND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . .0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . .–25°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7840 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD7840
PIN FUNCTION DESCRIPTION
Table I. Serial Data Modes
PIN CONFIGURATIONS
DIP/SSOPPLCC
for external use, it should he decoupled to AGND with a 200 Ω
resistor in series with a parallel combination of a 10 μF tantalum
capacitor and a 0.1 μF ceramic capacitor.
Figure 2.Internal Reference
EXTERNAL REFERENCE
In some applications, the user may require a system reference or
some other external reference to drive the AD7840 reference in-
put. Figure 3 shows how the AD586 5 V reference can be con-
ditioned to provide the 3 V reference required by the AD7840
REF IN. An alternate source of reference voltage for the
AD7840 in systems which use both a DAC and an ADC is to
use the REF OUT voltage of ADCs such as the AD7870 and
AD7871. A circuit showing this arrangement is shown in
Figure 20.
D/A SECTION
The AD7840 contains a 14-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. The simplified cir-
cuit diagram for the DAC section is shown in Figure 1. The
three MSBs of the data word are decoded to drive the seven
switches A–G. The 11 LSBs switch an 11-bit R-2R ladder struc-
ture. The output voltage from this converter has the same polar-
ity as the reference voltage, REF IN.
The REF IN voltage is internally buffered by a unity gain ampli-
fier before being applied to the D/A converter and the bipolar
bias circuitry. The D/A converter is configured and sealed for a
3 V reference and the device is tested with 3 V applied to REF
IN. Operating the AD7840 at reference voltages outside the5% tolerance range may result in degraded performance from
the part.
Figure 1.DAC Ladder Structure
INTERNAL REFERENCE
The AD7840 has an on-chip temperature compensated buried
Zener reference (see Figure 2) which is factory trimmed to 3 V10 mV. The reference voltage is provided at the REF OUT
pin. This reference can be used to provide both the reference
voltage for the D/A converter and the bipolar bias circuitry. This
is achieved by connecting the REF OUT pin to the REF IN pin
of the device.
AD7840
OP AMP SECTION
The output from the voltage mode DAC is buffered by a
noninverting amplifier. Internal scaling resistors on the AD7840
configure an output voltage range of ±3 V for an input reference
voltage of +3 V. The arrangement of these resistors around the
output op amp is as shown in Figure 1. The buffer amplifier is
capable of developing ±3 V across a 2 kΩ and 100 pF load to
ground and can produce 6 V peak-to-peak sine wave signals to a
frequency of 20 kHz. The output is updated on the falling edge
of the LDAC input. The amplifier settles to within 1/2 LSB of
its final value in typically less than 2.5 μs.
The small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the ampli-
fier is low with a figure of 30 nV/√Hz at a frequency of 1 kHz.
The broadband noise from the amplifier exhibits a typical peak-
to-peak figure of 150 μV for a 1 MHz output bandwidth. Figure
4 shows a typical plot of noise spectral density versus frequency
for the output buffer amplifier and for the on-chip reference.
Figure 4.Noise Spectral Density vs. Frequency
TRANSFER FUNCTION
The basic circuit configuration for the AD7840 is shown in Fig-
ure 5. Table II shows the ideal input code to output voltage re-
lationship for this configuration. Input coding to the DAC is 2s
complement with 1 LSB = FS/16,384 = 6 V/16,384 = 366 μV.
Figure 5.AD7840 Basic Connection Diagram
Table II.Ideal Input/Output Code Table
*Assuming REF IN = +3 V.
The output voltage can be expressed in terms of the input code,
N, using the following expression: OUT=2×N×REFIN
16384−8192≤N≤+8191
INTERFACE LOGIC INFORMATION
The AD7840 contains two 14-bit latches, an input latch and a
DAC latch. Data can be loaded to the input latch in one of two
basic interface formats. The first is a parallel 14-bit wide data
word; the second is a serial interface where 16 bits of data are
serially clocked into the input latch. In the parallel mode, CS
and WR control the loading of data. When the serial data format
is selected, data is loaded using the SCLK, SYNC and SDATA
serial inputs. Data is transferred from the input latch to the
DAC latch under control of the LDAC signal. Only the data in
the DAC latch determines the analog output of the AD7840.
Parallel Data Format
Table III shows the truth table for AD7840 parallel mode op-
eration. The AD7840 normally operates with a parallel input
data format. In this case, all 14 bits of data (appearing on data
inputs D13 (MSB) through D0 (LSB)) are loaded to the
AD7840 input latch at the same time. CS and WR control the
loading of this data. These control signals are level-triggered;
therefore, the input latch can be made transparent by holding
both signals at a logic low level. Input data is latched into the in-
put latch on the rising edge of CS or WR.
The DAC latch is also level triggered. The DAC output is nor-
mally updated on the falling edge of the LDAC signal. However,
both latches cannot become transparent at the same time.
Therefore, if LDAC is hardwired low, the part operates as fol-
lows; with LDAC low and CS and WR high, the DAC latch is
transparent. When CS and WR go low (with LDAC still low),
the input latch becomes transparent but the DAC latch is dis-
abled. When CS or WR return high, the input latch is locked
out and the DAC latch becomes transparent again and the DAC
output is updated. The write cycle timing diagram for parallel
data is shown in Figure 6. Figure 7 shows the simplified parallel
input control logic for the AD7840.
Table III.Parallel Mode Truth Table
X = Don’t Care
Figure 6.Parallel Mode Timing Diagram
Figure 7.AD7840 Simplified Parallel Input Control Logic
Serial Data Format
The serial data format is selected for the AD7840 by connecting
the CS/SERIAL line to –5 V. In this case, the WR/SYNC,
D13/SDATA, D12/SCLK, D11/FORMAT and D10/JUSTIFY
pins all assume their serial functions. The unused parallel inputs
should not be left unconnected to avoid noise pickup. Serial
data is loaded to the input latch under control of SCLK, SYNC
and SDATA. The AD7840 expects a 16-bit stream of serial data
on its SDATA input. Serial data must be valid on the falling
edge of SCLK. The SYNC input provides the frame synchroni-
zation signal which tells the AD7840 that valid serial data will
be available for the next 16 falling edges of SCLK. Figure 8
shows the timing diagram for serial data format.
Figure 8.Serial Mode Timing Diagram
Although 16 bits of data are clocked into the AD7840, only 14
bits go into the input latch. Therefore, two bits in the stream are
don’t cares since their value does not affect the input latch data.
The order and position in which the AD7840 accepts the 14 bits
of input data depends upon the FORMAT and JUSTIFY in-
puts. There are four different input data modes which can be
chosen (see Table I in the Pin Function Description section).
The first mode (M1) assumes that the first two bits of the input
data stream are don’t cares, the third bit is the LSB and the last
(or 16th bit) is the MSB. This mode is chosen by tying both the
FORMAT and JUSTIFY pins to a logic 0. The second mode
(M2; FORMAT = 0, JUSTIFY = 1) assumes that the first bit in
the data stream is the LSB, the fourteenth bit is the MSB and
the last two bits are don’t cares. The third mode (M3;
FORMAT= 1, JUSTIFY 0) assumes that the first two bits in
the stream are again don’t cares, the third bit is now the MSB
and the sixteenth bit is the LSB. The final mode (M4; FOR-
MAT = 1, JUSTIFY= 1) assumes that the first bit is the MSB,
the fourteenth bit is the LSB and the last two bits of the stream
are don’t cares.
AD7840
As in the parallel mode, the LDAC signal controls the loading
of data to the DAC latch. Normally, data is loaded to the DAC
latch on the falling edge of LDAC. However, if LDAC is held
low, then serial data is loaded to the DAC latch on the sixteenth
falling edge of SCLK. If LDAC goes low during the transfer of
serial data to the input latch, no DAC latch update takes place
on the falling edge of LDAC. If LDAC stays low until the serial
transfer is completed, then the update takes place on the six-
teenth falling edge of SCLK. If LDAC returns high before the
serial data transfer is completed, no DAC latch update takes
place. Figure 9 shows the simplified serial input control logic for
the AD7840.
Figure 9.AD7840 Simplified Serial Input Control Logic
AD7840 DYNAMIC SPECIFICATIONS
The AD7840 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as integral and differential nonlinearity. These ac specifications
are required for the signal processing applications such as
speech synthesis, servo control and high speed modems. These
applications require information on the DAC’s effect on the
spectral content of the signal it is creating. Hence, the param-
eters for which the AD7840 is specified include signal-to-noise
ratio, harmonic distortion and peak harmonics. These terms are
discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
DAC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (fs/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to noise ratio for a sine wave out-
put is given by
SNR = (6.02N + 1.76) dB(1)
where N is the number of bits. Thus for an ideal 14-bit con-
verter, SNR = 86 dB.
Figure 10 shows a typical 2048 point Fast Fourier Transform
(FFT) plot of the AD7840KN with an output frequency of
1 kHz and an update rate of 100 kHz. The SNR obtained from
this graph is 81.8 dB. It should be noted that the harmonics are
taken into account when calculating the SNR.
Figure 10.AD7840 FFT Plot
Effective Number of Bits
The formula given in (1) relates the SNR to the number of bits.
Rewriting the formula, as in (2) it is possible to get a measure of
performance expressed in effective number of bits (N). N=SNR−1.76
6.02(2)
The effective number of bits for a device can be calculated
directly from its measured SNR.
Harmonic Distortion
Harmonic distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7840, total harmonic distortion
(THD) is defined as
THD=20log
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic. The THD is also derived from the 2048-point
FFT plot.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the DAC output
spectrum (up to fs/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor the peak
will be a noise peak.
Testing the AD7840
A simplified diagram of the method used to test the dynamic
performance specifications is outlined in Figure 11. Data is
loaded to the AD7840 under control of the microcontroller and
associated logic at a 100 kHz update rate. The output of the
AD7840 is applied to a ninth order, 50 kHz, low-pass filter. The
output of the filter is in turn applied to a 16-bit accurate digi-
tizer. This digitizes the signal and the microcontroller generates
an FFT plot from which the dynamic performance of the
AD7840 can be evaluated.

Partno	Mfg	Dc	Qty	Available	Descript
AD7840		N/a	3	avai	Complete 14-Bit CMOS DAC