AD783AR-AD783JQ-AD783JR Fast Delivery |IC PHOENIX CO.,LIMITED

AD783AR ,Complete Very High Speed Sample-and-Hold AmplifierFEATURESAcquisition Time to 0.01%: 250 ns TypicalLow Power Dissipation: 95 mWLow Droop Rate: 0.02 m ..
AD783JQ ,Complete Very High Speed Sample-and-Hold AmplifierSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*PIN CONFIGURATIONWithSpec ..
AD783JR ,Complete Very High Speed Sample-and-Hold AmplifierSPECIFICATIONS (T to T with V = +5 V 6 5%, V = –5 V 6 5%, C = 50 pF, unless otherwise noted)MIN MAX ..
AD7840 ,Complete 14-Bit CMOS DACSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDEV to AGND . ..
AD7840AQ ,LC2MOS Complete 14-Bit DACspecifications in bold print are 100% production tested. All other times are sample tested at +25°C ..
AD7840ARS ,LC2MOS Complete 14-Bit DACspecifications, the AD7840 isLDAC signal. A fast data setup time of 21 ns allows direct specified f ..
ADM232A ,Part of a family of high speed RS-232 line drivers/receivers offering transmission rates up to 200 kB/sGENERAL DESCRIPTIONSHDNGNDThe ADM222, ADM232A, ADM242 are a family of high-speed* INTERNAL 400k PU ..
ADM232AAN ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTIONEN (ADM242)ADM2xxThe ADM222, ADM232A, ADM242 are a family of high speedSHDN (ADM ..
ADM232AANZ , High-Speed, 5 V, 0.1 F CMOS RS-232 Drivers/Receivers
ADM232AARN ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversSpecificationsTwo Drivers and Two Receivers 0.1µFVCCC1+On-Board DC-DC Converters+5V TO +10V0.1µFV+V ..
ADM232AARNZ-REEL , High-Speed, 5 V, 0.1 F CMOS RS-232 Drivers/Receivers
ADM232AARW ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversSpecificationsTwo Drivers and Two Receivers 0.1µFVCCC1+On-Board DC-DC Converters+5V TO +10V0.1µFV+V ..

AD783AR-AD783JQ-AD783JR
Complete Very High Speed Sample-and-Hold Amplifier
FUNCTIONAL BLOCK DIAGRAM
REV.AComplete Very High Speed
Sample-and-Hold Amplifier
FEATURES
Acquisition Time to 0.01%: 250 ns Typical
Low Power Dissipation: 95 mW
Low Droop Rate: 0.02 mV/ms
Fully Specified and Tested Hold Mode Distortion
Total Harmonic Distortion: –85 dB
Aperture Jitter: 50 ps Maximum
Internal Hold Capacitor
Self-Correcting Architecture
8-Pin Mini Cerdip and SOIC Packages
PRODUCT DESCRIPTION
The AD783 is a high speed, monolithic sample-and-hold
amplifier (SHA). The AD783 offers a typical acquisition time
of 250 ns to 0.01%. The AD783 is specified and tested for hold
mode total harmonic distortion with input frequencies up to
100 kHz. The AD783 is configured as a unity gain amplifier
and uses a patented self-correcting architecture that minimizes
hold mode errors and ensures accuracy over temperature. The
AD783 is self-contained and requires no external components
or adjustments.
The AD783 retains the held value with a droop rate of 0.02 μV/
μs. Excellent linearity and hold mode dc and dynamic perfor-
mance make the AD783 ideal for high speed 12- and 14-bit
analog-to-digital converters.
The AD783 is manufactured on Analog Devices’ ABCMOS
process which merges high performance, low noise bipolar
circuitry with low power CMOS to provide an accurate, high
speed, low power SHA.
The J grade device is specified for operation from 0°C to +70°C
and the A grade from –40°C to +85°C. The J and A grades are
available in 8-pin cerdip and SOIC packages. The military
temperature range version is specified for operation from –55°C
to +125°C and is available in an 8-pin cerdip package. For
details refer to the Analog Devices Military Products Databook or
AD783/883B data sheet.
*. Patent Number 4,962,325.
PRODUCT HIGHLIGHTSFast acquisition time (250 ns), low aperture jitter (20 ps) and
fully specified hold mode distortion make the AD783 an
ideal SHA for sampling systems.Low droop (0.02 μV/μs) and internally compensated hold
mode error result in superior system accuracy.Low power (95 mW typical), complete functionality and
small size make the AD783 an ideal choice for a variety of
high performance applications.The AD783 requires no external components or adjustments.The AD783 is an excellent choice as a front-end SHA for
high speed analog-to-digital converters such as the AD671,
AD7586, AD674B, AD774B, AD7572 and AD7672.Fully specified and tested hold mode distortion guarantees
the performance of the SHA in sampled data systems.
AD783–SPECIFICATIONS
DC SPECIFICATIONS
HOLD CHARACTERISTICS
ACCURACY CHARACTERISTICS
OUTPUT CHARACTERISTICS
INPUT CHARACTERISTICS
DIGITAL CHARACTERISTICS
TEMPERATURE RANGE
NOTESSpecified and tested over an input range of ±2.5 V.
Specifications subject to change without notice.
(TMIN to TMAX with VCC = +5 V 6 5%, VEE = –5 V 6 5%, CL = pF, unless otherwise noted)
AD783
HOLD MODE AC SPECIFICATIONS
NOTESfIN amplitude = 0 dB and fSAMPLE = 300 kHz unless otherwise indicated.
Specifications subject to change without notice.
(TMIN to TMAX with VCC = +5 V 6 5%, VEE = –5 V 6 5%, CL = 50 pF, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.
PIN CONFIGURATION
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD783 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
NOTES
AD783–Typical Characteristics
Power Supply Rejection Ratio vs. Frequency
Bias Current vs. Input Voltage
Droop Rate vs. Temperature, VIN = 0 V
Acquisition Time (to 0.01%) vs. Input Step Size
DEFINITIONS OF SPECIFICATIONS
Acquisition Time—The length of time that the SHA must
remain in the sample mode in order to acquire a full-scale input
step to a given level of accuracy.
Small Signal Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 100 mV p-p sine wave.
Full Power Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 5 V p-p sine wave.
Effective Aperture Delay—The difference between the switch
delay and the analog delay of the SHA channel. A negative
number indicates that the analog portion of the overall delay is
greater than the switch portion. This effective delay represents
the point in time, relative to the hold command, that the input
signal will be sampled.
Aperture Jitter—The variations in aperture delay for
successive samples. Aperture jitter puts an upper limit on the
maximum frequency that can be accurately sampled.
Hold Settling Time—The time required for the output to
settle to within a specified level of accuracy of its final held value
after the hold command has been given.
Droop Rate—The drift in output voltage while in the hold
mode.
Feedthrough—The attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
Hold Mode Offset—The difference between the input signal
and the held output. This offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of 0 V.
Sample Mode Offset—The difference between the input and
output signals when the SHA is in the sample mode.
Nonlinearity—The deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of –2.5 V and +2.5 V.
Gain Error—Deviation from a gain of +1 on the transfer
function of input vs. held output.
Power Supply Rejection Ratio—A measure of change in the
held output voltage for a specified change in the positive or
negative supply.
Sampled DC Uncertainty—The internal rms SHA noise that
is sampled onto the hold capacitor.
Hold Mode Noise—The rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
Total Output Noise—The total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms
summation of the sampled dc uncertainty and the hold mode
noise.
Output Drive Current—The maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.5 mV.
Signal-To-Noise and Distortion (S/N+D) Ratio—S/N+D is
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Total Harmonic Distortion (THD)—THD is the ratio of the
rms sum of the first six harmonic components to the rms value
of the measured input signal and is expressed in decibels.
Intermodulation Distortion (IMD)—With inputs consisting
of sine waves at two frequencies, fa and fb, any device with
nonlinearities will create distortion products, of order (m+n), at
sum and difference frequency of mfa±nfb, where m, n = 0, 1, 2,... Intermodulation terms are those for which m or n is not
equal to zero. For example, the second order terms are (fa+fb)
and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),
(fa+2fb) and (fa–2fb). The IMD products are expressed as the
decibel ratio of the rms sum of the measured input signals to the
rms sum of the distortion terms. The two signals are of equal
amplitude, and peak value of their sums is –0.5 dB from full
scale. The IMD products are normalized to a 0 dB input signal.
FUNCTIONAL DESCRIPTION
The AD783 is a complete, high speed sample-and-hold
amplifier that provides high speed sampling to 12-bit accuracy
in 250 ns.
The AD783 is completely self-contained, including an on-chip
hold capacitor, and requires no external components or adjust-
ments to perform the sampling function. Both input and output
are treated as a single-ended signal, referred to common.
The AD783 utilizes a proprietary circuit design which includes a
self-correcting architecture. This sample-and-hold circuit
corrects for internal errors after the hold command has been
given, by compensating for amplifier gain and offset errors, and
charge injection errors. Due to the nature of the design, the
SHA output in the sample mode is not intended to provide an
accurate representation of the input. However, in hold mode,
the internal circuitry is reconfigured to produce an accurately
held version of the input signal. Below is a block diagram of the
AD783.
AD783
DYNAMIC PERFORMANCE
The AD783 is compatible with 12-bit A-to-D converters in
terms of both accuracy and speed. The fast acquisition time, fast
hold settling time and good output drive capability allow the
AD783 to be used with high speed, high resolution A-to-D
converters like the AD671 and AD7586. The AD783’s fast
acquisition time provides high throughput rates for multichannel
data acquisition systems. Typically, the AD783 can acquire a
5 V step in less than 250 ns. Figure 1 shows the settling
accuracy as a function of acquisition time.
Figure 1.VOUT Settling vs. Acquisition Time
The hold settling determines the required time, after the hold
command is given, for the output to settle to its final specified
accuracy. The typical settling behavior of the AD783 is 150 ns.
The settling time of the AD783 is sufficiently fast to allow the
SHA, in most cases, to directly drive an A-to-D converter
without the need for an added “start convert” delay.
HOLD MODE OFFSET
The dc accuracy of the AD783 is determined primarily by the
hold mode offset. The hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. The hold mode offset arises
from a voltage error introduced onto the hold capacitor by
charge injection of the internal switches. The nominal hold
mode offset is specified for a 0 V input condition. Over the in-
put range of –2.5 V to +2.5 V, the AD783 is also characterized
for an effective gain error and nonlinearity of the held value, as
shown in Figure 2. As indicated by the AD783 specifications,
the hold mode offset is very stable over temperature.
Figure 2.
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accom-
plished through the A-to-D itself or by an external amplifier
with offset nulling capability (e.g., AD711). The offset will
change less than 0.5 mV over the specified temperature range.
SUPPLY DECOUPLING AND GROUNDING
CONSIDERATIONS
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from
excessive high frequency noise (ripple). The supply connection
to the AD783 should also be capable of delivering transient
currents to the device. To achieve the specified accuracy and
dynamic performance, decoupling capacitors must be placed
directly at both the positive and negative supply pins to com-
mon. Ceramic type 0.1 μF capacitors should be connected from
VCC and VEE to common.

Partno	Mfg	Dc	Qty	Available	Descript
AD783AR	AD	N/a	150	avai	Complete Very High Speed Sample-and-Hold Amplifier
AD783JQ	AD	N/a	44	avai	Complete Very High Speed Sample-and-Hold Amplifier
AD783JR	ADI	N/a	10	avai	Complete Very High Speed Sample-and-Hold Amplifier