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AD7839AS
Octal 13-Bit, Parallel Input, Voltage-Output DAC
REV.0
Octal 13-Bit, Parallel Input,
Voltage-Output DAC
FUNCTIONAL BLOCK DIAGRAM
DB12
DB0
LDAC
VCCVSSVDD
VREF(+)
VREF(–)
DUTGND
DUTGND
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
DUTGND
DUTGND
VREF(–)
CDEF
VREF(+)
CDEF
VREF(–)
VREF(+)
GNDCLR
FEATURES
Eight 13-Bit DACs in One Package
Voltage Outputs
Offset Adjust for Each DAC Pair
Reference Range of 65 V
Maximum Output Voltage Range of 610 V
Clear Function to User-Defined Voltage
44-Lead MQFP Package
APPLICATIONS
Automatic Test Equipment
Process Control
General Purpose Instrumentation
GENERAL DESCRIPTIONThe AD7839 contains eight 13-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of –10 V
from reference voltages of –5 V.
The AD7839 accepts 13-bit parallel loaded data from the exter-
nal bus into one of the input registers under the control of the
WR, CS and DAC channel address pins, A0–A2.
The DAC outputs are updated on reception of new data into
the DAC registers. All the outputs may be updated simulta-
neously by taking the LDAC input low.
Each DAC output is buffered with a gain-of-two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.
The AD7839 is available in a 44-lead MQFP package.
AD7839–SPECIFICATIONS
(VCC = +5 V 6 5%; VDD = +15 V 6 5%; VSS = –15 V 6 5%; GND = DUTGND = 0 V;
RL = 5 kV and CL = 50 pF to GND, TA1 = TMIN to TMAX, unless otherwise noted.)REFERENCE INPUTS
DIGITAL INPUTS
NOTESTemperature range for A Version: –40°C to +85°CGuaranteed by characterization. Not production tested.The AD7839 is functional with power supplies of –12 V – 10% with reduced output range. At 12 V it is recommended to restrict reference range to –4 V due to
output amplifier headroom limitations
Specifications subject to change without notice.
AD7839
(These characteristics are included for Design Guidance and are not subject
to production testing.)AC PERFORMANCE CHARACTERISTICSSpecifications subject to change without notice.
TIMING SPECIFICATIONS1, 2t10
NOTESAll input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
t10
LDAC
CLR
A0, A1, A2
DATA
VOUT
VOUT
t11
(VCC = +5 V 6 5%; VDD = +15 V 6 5%; VSS = –15 V 6 5%; GND = DUTGND = 0 V)
AD7839
ABSOLUTE MAXIMUM RATINGS1, 2(TA = +25°C unless otherwise noted)
VCC to GND3 . . . . . . . . . . . . . . .–0.3 V, +7 V or VDD + 0.3 V
(Whichever Is Lower)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V, –17 V
Digital Inputs to GND . . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
VREF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +18 V
VREF(+) to GND . . . . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
VREF(–) to GND . . . . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
DUTGND to GND . . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
VOUT (A–H) to GND . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . .+150°C
MQFP Package
Power Dissipation . . . . . . . . . . . . . . . . . . (TJ max – TA)/qJAJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4000 V
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.VCC must not exceed VDD by more than 0.3 V. If it is possible for this to happen
during power supply sequencing, the following diode protection scheme will ensure
protection.
ORDERING GUIDE*S = Plastic Quad Flatpack (MQFP).
PIN CONFIGURATION
DUTGND_GH
VOUTH
VREF(–)GH
VREF(+)GH
VSS
CLR
DB12
DUTGND_AB
VOUTA
VREF(–)AB
VREF(+)AB
VDD
VSS
LDAC
DB11
DB10
DB9
DB8
DB4
OUT
OUT
DUTGND_CD
OUT
OUT
DUTGND_EFV
OUT
OUT
DB7DB5DB6DB2
GND
DB0
DB1
DB3
REF
(–)CDEF
REF
(+)CDEF
IN4148
VDDVCC
PIN FUNCTION DESCRIPTIONS5VDD
AD7839
TERMINOLOGY
Relative AccuracyRelative accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after adjust-
ing for zero error and full-scale error and is normally expressed
in Least Significant Bits.
Differential NonlinearityDifferential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DC CrosstalkAlthough the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or another of the chan-
nel outputs.
The eight DAC outputs are buffered by op amps that share
common VDD and VSS power supplies. If the dc load current
changes in one channel (due to an update), this can result in a
further dc change in one or another of the channel outputs. This
effect is most obvious at high load currents and reduces as the
load currents are reduced. With high impedance loads the effect
is virtually unmeasurable.
Output Voltage Settling TimeThis is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch ImpulseThis is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-secs. It is measured with VREF(+) = +5 V and
VREF(–) = –5 V and the digital inputs toggled between 0FFFH and
1000H.
Channel-to-Channel IsolationChannel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input that appears at the out-
put of another DAC. It is expressed in dBs.
DAC-to-DAC CrosstalkDAC-to-DAC crosstalk is defined as the glitch impulse that
appears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-secs.
Digital CrosstalkThe glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-secs.
Digital FeedthroughWhen the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. This noise is digital feedthrough.
DC Output ImpedanceThis is the effective output source resistance. It is dominated by
Full-Scale ErrorThis is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 VREF(+) – 1 LSB.
Zero-Scale ErrorZero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to 2 VREF(–). Zero-
scale error is mainly due to offsets in the output amplifier.
Gain ErrorGain Error is defined as (Full-Scale Error) – (Zero-Scale Error).
GENERAL DESCRIPTION
DAC Architecture—GeneralEach channel consists of a straight 13-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to twice the
reference span of VREF(+) – VREF(–). The DAC coding is straight
binary; all 0s produces an output of 2 VREF(–); all 1s produces
an output of 2 VREF(+) – 1 LSB.
The analog output voltage of each DAC channel reflects the
contents of its own DAC register. Data is transferred from the
external bus to the input register of each DAC on a per channel
basis.
Bringing the CLR line low switches all the signal outputs, VOUTA
to VOUTH, to the voltage level on the DUTGND pin. When the
CLR signal is brought back high, the output voltages from the
DACs will reflect the data stored in the relevant DAC registers.
Data Loading to the AD7839Data is loaded into the AD7839 in straight parallel 13-bit wide
words.
The DAC output voltages, VOUTA – VOUTH are updated to
reflect new data in the DAC registers.
The actual input register being written to is determined by the
logic levels present on the device’s address lines, as shown in
Table I.
Table I.Address Line Truth Table
