AD7837BR ,LC2MOS Complete, Dual 12-Bit MDACsFEATURES FUNCTIONAL BLOCK DIAGRAMSTwo 12-Bit MDACs with Output AmplifiersVDD4-Quadrant Multiplicati ..
AD7837SQ ,LC2MOS Complete, Dual 12-Bit MDACsFEATURES FUNCTIONAL BLOCK DIAGRAMSTwo 12-Bit MDACs with Output AmplifiersVDD4-Quadrant Multiplicati ..
AD7839AS ,Octal 13-Bit, Parallel Input, Voltage-Output DACCHARACTERISTICSOutput Voltage Swing – 10 V min 2 · (V (–) + [V (+) – V (–)] · D) – VREF REF REF DUT ..
AD783AR ,Complete Very High Speed Sample-and-Hold AmplifierFEATURESAcquisition Time to 0.01%: 250 ns TypicalLow Power Dissipation: 95 mWLow Droop Rate: 0.02 m ..
AD783JQ ,Complete Very High Speed Sample-and-Hold AmplifierSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*PIN CONFIGURATIONWithSpec ..
AD783JR ,Complete Very High Speed Sample-and-Hold AmplifierSPECIFICATIONS (T to T with V = +5 V 6 5%, V = –5 V 6 5%, C = 50 pF, unless otherwise noted)MIN MAX ..
ADM231LAR ,+5 V Powered CMOS RS-232 Drivers/Receiversapplications where ±12 V is not available. The ADM223, These converters convert the +5 V input pow ..
ADM231LJN ,+5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION All members of the ADM230L family, except the ADM231LThe ADM2xx family of line ..
ADM231LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSPECIFICATIONS32L, 34L, 36L, 38L, 39L, 41L);V = +5 V 6 5% (ADM230L, 33L, 35L, 37L); V+ = 7.5 V to 1 ..
ADM232A ,Part of a family of high speed RS-232 line drivers/receivers offering transmission rates up to 200 kB/sGENERAL DESCRIPTIONSHDNGNDThe ADM222, ADM232A, ADM242 are a family of high-speed* INTERNAL 400k PU ..
ADM232AAN ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTIONEN (ADM242)ADM2xxThe ADM222, ADM232A, ADM242 are a family of high speedSHDN (ADM ..
ADM232AANZ , High-Speed, 5 V, 0.1 F CMOS RS-232 Drivers/Receivers
AD7837AN-AD7837AQ-AD7837AR-AD7837BN-AD7837BR-AD7837SQ-AD7847AN-AD7847AR-AD7847BN
LC2MOS Complete, Dual 12-Bit MDACs
REV.C
LC2MOS
Complete, Dual 12-Bit MDACs
FUNCTIONAL BLOCK DIAGRAMS
AGNDA
LDAC
RFBA
VOUTA
DGND
AGNDB
RFBB
VOUTB
VSS
VDD
VREFA
VREFB
DB0
DB7
AGNDA
CSB
CSA
VOUTA
DGND
AGNDB
VOUTB
VSS
VDD
VREFA
VREFB
DB0
DB11
GENERAL DESCRIPTIONThe AD7837/AD7847 is a complete, dual, 12-bit multiplying
digital-to-analog converter with output amplifiers on a mono-
lithic CMOS chip. No external user trims are required to
achieve full specified performance.
Both parts are microprocessor compatible, with high speed data
latches and interface logic. The AD7847 accepts 12-bit parallel
data which is loaded into the respective DAC latch using the
WR input and a separate Chip Select input for each DAC. The
AD7837 has a double-buffered 8-bit bus interface structure
with data loaded to the respective input latch in two write opera-
tions. An asynchronous LDAC signal on the AD7837 updates
the DAC latches and analog outputs.
The output amplifiers are capable of developing ±10 V across a
2 kΩ load. They are internally compensated with low input off-
set voltage due to laser trimming at wafer level.
The amplifier feedback resistors are internally connected to
VOUT on the AD7847.
The AD7837/AD7847 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
A novel low leakage configuration (U.S. Patent No. 4,590,456)
ensures low offset errors over the specified temperature range.
PRODUCT HIGHLIGHTSThe AD7837/AD7847 is a dual, 12-bit, voltage-out MDAC
on a single chip. This single chip design offers considerable
space saving and increased reliability over multichip designs.
2. The AD7837 and the AD7847 provide a fast versatile inter-
face to 8-bit or 16-bit data bus structures.
FEATURES
Two 12-Bit MDACs with Output Amplifiers
4-Quadrant Multiplication
Space-Saving 0.3", 24-Lead DIP and 24-Terminal
SOIC Package
Parallel Loading Structure: AD7847
(8 + 4) Loading Structure: AD7837
APPLICATIONS
Automatic Test Equipment
Function Generation
Waveform Reconstruction
Programmable Power Supplies
Synchro Applications
AD7837/AD7847–SPECIFICATIONS1(VDD = +15 V � 5%, VSS = –15 V � 5%, AGNDA = AGNDB = DGND
= O V. VREFA = VREFB = +10 V, RL = 2 k�, CL = 100 pF [VOUT connected to RFB AD7837]. All specifications TMIN to TMAX unless otherwise noted.)NOTES
TIMING CHARACTERISTICS1, 2, 3NOTESAll input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 3 and 5.Guaranteed by design and characterization, not production tested.AD7837 only.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to DGND, AGNDA, AGNDB . . . . . . .–0.3 V to +17 V
VSS1 to DGND, AGNDA, AGNDB . . . . . . .+0.3 V to –17 V
VREFA, VREFB to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V
AGNDA, AGNDB to DGND . . . . . . .–0.3 V to VDD + 0.3 V
VOUTA2, VOUTB2 to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V
RFBA3, RFBB3 to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial/Industrial (A, B Versions) . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . .300°C
Power Dissipation (Any Package) to +75°C . . . . . .1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
NOTESIf VSS is open circuited with VDD and either AGND applied, the VSS pin will float
positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a
Schottky diode connected between VSS and AGND (cathode to AGND) ensures
the Maximum Ratings will be observed.The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded.AD7837 only.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
ORDERING GUIDENOTESTo order MIL-STD-883, Class B processed parts, add /883B to part number.N = Plastic DIP; Q = Cerdip; R = SOIC.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
(VDD = +15 V � 5%, VSS = –15 V � 5%, AGNDA = AGNDB = DGND = O V)
AD7837/AD7847
TERMINOLOGY
Relative Accuracy (Linearity)Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints. It is measured after
allowing for zero and full-scale errors and is expressed in LSBs
or as a percentage of full-scale reading.
Differential NonlinearityDifferential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB or less
over the operating temperature range ensures monotonicity.
Zero Code Offset ErrorZero code offset error is the error in output voltage from VOUTA
or VOUTB with all 0s loaded into the DAC latches. It is due to a
combination of the DAC leakage current and offset errors in the
output amplifier.
Gain ErrorGain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded. It does
not include offset error.
Total Harmonic DistortionThis is the ratio of the root-mean-square (rms) sum of the har-
monics to the fundamental, expressed in dBs.
Multiplying Feedthrough ErrorThis is an ac error due to capacitive feedthrough from the VREF
input to VOUT of the same DAC when the DAC latch is loaded
with all 0s.
Channel-to-Channel IsolationThis is an ac error due to capacitive feedthrough from the VREF
input on one DAC to VOUT on the other DAC. It is measured
with the DAC latches loaded with all 0s.
Digital FeedthroughDigital feedthrough is the glitch impulse injected from the digi-
tal inputs to the analog output when the data inputs change state,
but the data in the DAC latches is not changed.
For the AD7837, it is measured with LDAC held high. For the
AD7847, it is measured with CSA and CSB held high.
Digital CrosstalkDigital crosstalk is the glitch impulse transferred to the output
of one converter due to a change in digital code on the DAC
latch of the other converter. It is specified in nV secs.
Digital-to-Analog Glitch ImpulseThis is the voltage spike that appears at the output of the DAC
when the digital code changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs and is
measured for a 1 LSB change around the major carry transition
(0111 1111 1111 to 1000 0000 0000 and vice versa).
Unity Gain Small Signal BandwidthThis is the frequency at which the small signal voltage output
from the output amplifier is 3 dB below its dc level. It is mea-
sured with the DAC latch loaded with all 1s.
Full Power BandwidthThis is the maximum frequency for which a sinusoidal input
signal will produce full output at rated load with a distortion
less than 3%. It is measured with the DAC latch loaded with
all 1s.
AD7837 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS)2RFBA
3VREFA
4VOUTA
6VDD
7VSS
9VOUTB
AD7847 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS)
AD7837 PIN CONFIGURATION AD7847 PIN CONFIGURATION
DIP AND SOIC DIP AND SOIC
AD7837/AD7847–Typical Performance GraphsFigure 1.Frequency Response
Figure 4.Linearity vs. Power Supply
Figure 7.Multiplying Feedthrough
Error vs. Frequency
Figure 2.Output Voltage Swing vs.
Resistive Load
Figure 5.Noise Spectral Density vs.
Frequency
Figure 8.Large Signal Pulse
Response
CODE
ERROR
LSB
–0.4Figure 3.DAC-to-DAC Linearity
Matching
Figure 6.THD vs. Frequency
Figure 9.Small Signal Pulse
Response
