AD7836AS Fast Delivery |IC PHOENIX CO.,LIMITED

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AD7836AS
LC2MOS Quad 14-Bit DAC
REV.ALC2MOS
Quad 14-Bit DAC
FEATURES
Four 14-Bit DACs in One Package
Voltage Outputs
Separate Offset Adjust for Each Output
Reference Range of �5 V
Maximum Output Voltage Range of �10 V
Clear Function to User-Defined Code
44-Pin MQFP Package
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7836 contains four 14-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of ±10 V
from reference voltages of ±5 V.
The AD7836 accepts 14-bit parallel loaded data from the exter-
nal bus into one of the input latches under the control of the
WR, CS and DAC channel address pins, A0–A2.
The DAC outputs are updated individually, on reception of new
data. In addition, the SEL input can be used to apply the user
programmed value in DAC Register E to all DACs, thus setting
all DAC output voltages to the same level. The contents of the
DAC data registers are not affected by the SEL input.
Each DAC output is buffered with a gain of two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.
The AD7836 is available in a 44-lead MQFP package.
FUNCTIONAL BLOCK DIAGRAM
DUTGND D
DUTGND C
VOUTD
DUTGND B
VOUTC
DUTGND A
VOUTB
VOUTA
DB0
DB13
VCCVSSVDDVREF(+)A
SELAGNDDGND
VREF(–)AVREF(+)BVREF(–)B
VREF(+)DVREF(–)DVREF(+)CVREF(–)CCLR
AD7836–SPECIFICATIONS
(VCC = +5 V � 5%; VDD = +15 V � 5%; VSS = –15 V � 5%; AGND = DGND = DUTGND
= 0 V; RL = 5 k� and CL = 50 pF to GND, TA1 = TMIN to TMAX, unless otherwise noted)
NOTESTemperature range for A Version: –40°C to +85°CGuaranteed by design.
(These characteristics are included for Design Guidance and are not
subject to production testing.)AC PERFORMANCE CHARACTERISTICS
TIMING SPECIFICATIONS1
NOTESAll input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
(VCC = +5 V � 5%; VDD = +15 V � 5%; VSS = –15 V � 5%; AGND = DGND = 0 V)
Figure 1.Timing Diagram
AD7836
ORDERING GUIDE
*S = Plastic Quad Flatpack (MQFP).
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VCC to DGND . . . . . . . . . . . . . . .–0.3 V, +7 V or VDD + 0.3 V
(Whichever Is Lower)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V, –17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +0.3 V
Digital Inputs to DGND . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
VREF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +18 V
VREF(+) to AGND . . . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
VREF(–) to AGND . . . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
DUTGND to AGND . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
VOUT (A–D) to AGND . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
MQFP Package, Power Dissipation . . . . . . . . . . . . . .480 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7836 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN DESCRIPTION
VREF(+)C, VREF(–)C
DUTGND A
DUTGND B
DUTGND C
DUTGND D
SEL
PIN CONFIGURATION
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DGND
VCC
CLR
VOUTC
VREF(–)C
VREF(+)C
AGND
VDD
VSS
VREF(+)A
VREF(–)A
VOUTA
DUTGND CV
REF
(+)D
REF
OUT
DUTGND D
DB13DB12DB11DB10DB9DB8
REF
(+)B
REF
OUTA1A0
SEL
AD7836
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after adjusting for
zero error and full-scale error and is normally expressed in Least
Significant Bits or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DC Crosstalk
Although the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or other of the channel
outputs.
The four DAC outputs are buffered by op amps that share com-
mon VDD and VSS power supplies. If the dc load current changes
in one channel (due to an update), this can result in a further dc
change in one or other channel outputs. This effect is most ob-
vious at high load currents and reduces as the load currents are
reduced. With high impedance loads the effect is virtually
unmeasurable.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output when
the inputs change state. It is specified as the area of the glitch in
nV-secs. It is measured with VREF(+) = +5 V and VREF(–) = –5 V
and the digital inputs toggled between 1FFFHEX and 8000H.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DACs reference input that appears at the output
of the other DAC. It is expressed in dBs.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that ap-
pears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s
loaded into the DAC latch, should be 2 VREF(+) – 1 LSB. Full-
scale error does not include zero-scale error.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to 2 VREF(–). Zero-
scale error is mainly due to offsets in the output amplifier.
Gain Error
Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error).
GENERAL DESCRIPTION
DAC Architecture—General
Each channel consists of a segmented 14-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to twice the
reference span of VREF(+) – VREF(–). The DAC coding is
straight binary; all 0s produces an output of 2 VREF(–); all 1s
produces an output of 2 VREF(+) – 1 LSB.
The analog output voltage of each DAC channel reflects the
contents of its own DAC latch. Data is transferred from the ex-
ternal bus to the input register of each DAC latch on a per
channel basis. The AD7836 has a feature whereby using the A2
pin, data can be transferred from the input data bus to all four
input registers simultaneously.
Bringing the CLR line low switches all the signal outputs,
VOUTA to VOUTD, to the voltage level on the DUTGND pin.
When CLR signal is brought back high the output voltages from
the DACs will reflect the data stored in the relevant DAC
registers.
Data Loading to the AD7836
Data is loaded into the AD7836 in straight parallel 14-bit wide
words.
The DAC output voltages, VOUTA–VOUTD are updated to
reflect new data in the DAC input registers.
The actual DAC input register that is being written to is deter-
mined by the logic levels present on the devices address lines, as
shown in Table I.
Table I.Address Line Truth Table

Partno	Mfg	Dc	Qty	Available	Descript
AD7836AS	ADI	N/a	200	avai	LC2MOS Quad 14-Bit DAC