AD7834AN-AD7834AR-AD7834BR-AD7835AS Fast Delivery |IC PHOENIX CO.,LIMITED

AD7834BR ,LC2MOS Quad 14-Bit DACGENERAL DESCRIPTIONFour 14-Bit DACs in One Package The AD7834 and AD7835 contain four 14-bit DACs o ..
AD7835AS ,LC2MOS Quad 14-Bit DACSPECIFICATIONSA MIN MAXParameter A B S Units Test Conditions/CommentsACCURACYResolution 14 14 14 Bi ..
AD7835AS ,LC2MOS Quad 14-Bit DACSPECIFICATIONS CC DD SSParameter Limit at T T Units DescriptionMIN, MAXAD7834 Specific2t 100 ns min ..
AD7836AS ,LC2MOS Quad 14-Bit DACAPPLICATIONS data. In addition, the SEL input can be used to apply the userProcess Control programm ..
AD7836ASZ , LC2MOS Quad 14-Bit DAC
AD7837AN ,LC2MOS Complete, Dual 12-Bit MDACsSpecifications subject to change without notice.–2–REV. CAD7837/AD78471, 2, 3TIMING
ADM222ARZ , High-Speed, 5 V, 0.1 F CMOS RS-232 Drivers/Receivers
ADM230LAN ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*Thermal Impedance, θJA(T = ..
ADM230LAR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications120 kB/s Data Rate1 16C1+ +5V TO +10V VCCOn-Board DC-DC Converters 1m F 1m F 1m FVOLT ..
ADM230LJR ,+5 V Powered CMOS RS-232 Drivers/ReceiversAPPLICATIONS8 R2R2 9 R2OUT INComputersGNDADM232LPeripherals15ModemsPrinters *INTERNAL 400kW PULL-UP ..
ADM230LJR ,+5 V Powered CMOS RS-232 Drivers/Receivers+5 V PoweredaCMOS RS-232 Drivers/ReceiversADM223/ADM230L–ADM241LADM232L TYPICAL OPERATING CIRCUIT
ADM231LAR ,+5 V Powered CMOS RS-232 Drivers/Receiversapplications where ±12 V is not available. The ADM223, These converters convert the +5 V input pow ..

AD7834AN-AD7834AR-AD7834BR-AD7835AS
LC2MOS Quad 14-Bit DAC
REV.ALC2MOS
Quad 14-Bit DAC
FEATURES
Four 14-Bit DACs in One Package
AD7834—Serial Loading
AD7835—Parallel 8-/14-Bit Loading
Voltage Outputs
Power-On Reset Function
Max/Min Output Voltage Range of +/–8.192 V
Maximum Output Voltage Span of 14 V
Common Voltage Reference Inputs
User Assigned Device Addressing
Clear Function to User-Defined Voltage
Surface Mount Packages
AD7834—28-Pin SO, DIP and Cerdip
AD7835—44-Pin PQFP and PLCC
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output volt-
ages in the range of ±8.192 V with a maximum span of 14 V.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading
0s, into one of the input latches via DIN, SCLK and FSYNC.
The AD7834 has five dedicated package address pins, PA0–
PA4, that can be wired to AGND or VCC to permit up to 32
AD7834s to be individually addressed in a multipackage
application.
The AD7835 can accept either 14-bit parallel loading or
double-byte loading, where right-justified data is loaded in one
8-bit and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF and DAC channel address pins, A0–A2.
With either device, the LDAC signal can be used to update
either all four DAC outputs simultaneously or individually,
on reception of new data. In addition, for either device, the
asynchronous CLR input can be used to set all signal outputs,
VOUT1–VOUT4, to the user-defined voltage level on the Device
Sense Ground pin, DSG. On power-on, before the power sup-
plies have stabilized, internal circuitry holds the DAC output
voltage levels to within ±2 V of the DSG potential. As the sup-
plies stabilize, the DAC output levels move to the exact DSG
potential (assuming CLR is exercised).
The AD7834 is available in 28-pin 0.3" SO and 0.6" DIP pack-
ages, and the AD7835 is available in a 44-pin PQFP package
and a 44-pin PLCC package.
AD7835 FUNCTIONAL BLOCK DIAGRAM
AD7834 FUNCTIONAL BLOCK DIAGRAM
VCCVDDVSSVREF(–)VREF(+)
VOUT 1PAEN
PA0
PA1
PA2
PA3
PA4
FSYNC
DIN
SCLK
VOUT 2
VOUT 3
VOUT 4
AGNDDGNDLDACDSG
CLR
AD7834/AD7835–SPECIFICATIONS
(VCC = +5 V ± 5%; VDD = +15 V ± 5%; VSS = –15 V ± 5%; AGND =
DGND = 0 V; TA1 = TMIN to TMAX, unless otherwise noted)
(These characteristics are included for Design Guidance and are not
subject to production testing. )AC PERFORMANCE CHARACTERISTICS
NOTES
TIMING SPECIFICATIONS1
AD7834 Specific
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
(VCC = +5 V ± 5%; VDD = +15 V ± 5%; VSS = –15 V ± 5%; AGND = DGND = 0 V)
Figure 2.AD7835 Timing Diagram
t1
LDAC
(SIMULTANEOUS
UPDATE)
LDAC
(PRE-CHANNEL
UPDATE)
1ST
CLK
2ND
CLK
24TH
CLK
SCLK
DIN
FSYNC
Figure 1.AD7834 Timing Diagram
AD7834/AD7835
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VCC to DGND . . . . . . . . . . . . . . .–0.3 V, +7 V or VDD + 0.3 V
(Whichever Is Lower)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V, –17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
VREF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +18 V
VREF(+) to AGND . . . . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
VREF(–) to AGND . . . . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
DSG to AGND . . . . . . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
VOUT (1–4) to AGND . . . . . . . . . . . .VSS – 0.3 V, VDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version). . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .+75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+260°C
Cerdip Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .+52°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+300°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7834/AD7835 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
NOTESR = Small Outline IC (SOIC); N = Plastic DIP; Q = Cerdip; S = Plastic Quad Flatpack (PQFP);
P = Plastic Leaded Chip Carrier (PLCC).Contact Sales Office for availability.
SOIC Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .+75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
PQFP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
PLCC Package
θJA Thermal Impedance. . . . . . . . . . . . . . . . . . . . . .+55°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
Power Dissipation (Any Package) . . . . . . . . . . . . . . . .480 mW
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch up.
AD7834 PIN DESCRIPTION
VSS
VDD
DGND
AGND
VREF(+)
PIN CONFIGURATION
DIP AND SOIC
VSS
AGND
DSG
VREF(–)
VREF(+)
VOUT1
VDDNC
VOUT2
VOUT4
DGND
VCC
SCLKLDAC
CLR
VOUT3
DIN
PA0
FSYNC
PAEN
AD7834/AD7835
AD7835 PIN DESCRIPTION
VDD
DGND
AGND
VREF(+)A, VREF(–)A
VREF(+)B, VREF(–)B
DB0
A0, A1, A2
DSGB
PIN CONFIGURATIONS
PQFP PLCC
DB4DB5DB6DB1
DGND
DB0DB2DB3
DSGB
VOUT3
VOUT4
DB13
DB12
DB11
DSGA
VOUT1
VOUT2
NC = NO CONNECT
CLR
LDAC
BYSHF
DB10
DB9
DB8
DB7V
REF
(+)AV
AGNDNCV
REF
(+)B
REF
(–)AV
REF
(–)B
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
DSGB
VOUT3
VOUT4
DB13
DB12
DB11
AD7835
DB1
DGND
DB0DB2DB3DB4
DB5
DB6
DSGA
VOUT1
VOUT2
NC = NO CONNECT
CLR
LDAC
BYSHF
DB10
DB9
DB8
DB7V
REF
(–)A
REF
(+)AV
AGNDNCNCV
(+)B
REF
(–)B
TERMINOLOGY
Relative Accuracy
Relative Accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after adjusting for
zero error and full-scale error and is normally expressed in Least
Significant Bits or as a percentage of full-scale reading.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DC Crosstalk
Although the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or other of the channel
outputs.
The four DAC outputs are buffered by op amps that share com-
mon VDD and VSS power supplies. If the dc load current changes
in one channel (due to an update), this can result in a further dc
change in one or other channel outputs. This effect is most ob-
vious at high load currents and reduces as the load currents are
reduced. With high impedance loads the effect is virtually
unmeasurable.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output when
the inputs change state. It is specified as the area of the glitch in
nV-secs. It is measured with the reference inputs connected to 0 V
signal from one DACs reference input which appears at the out-
put of the other DAC. It is expressed in dBs.
The AD7834 has no specification for Channel-to-channel isola-
tion because it has one reference for all DACs. Channel-to-
channel isolation is specified for the AD7835.
DAC-to-DAC Crosstalk
DAC-to-DAC Crosstalk is defined as the glitch impulse that ap-
pears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s
loaded into the DAC latch, should be VREF(+) – 1 LSB. Full-
Scale Error does not include Zero-Scale Error.
Zero-Scale Error
Zero-Scale Error is the error in the DAC output voltage when
all 0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to VREF(–). Zero-
AD7834/AD7835–Typical Performance Characteristics
CODE/1000
INL – LSBs
–0.816468101214
Figure 3.Typical INL Plot
VREF(+) – Volts
INL – LSBs
0.052.55
Figure 6.Typical INL vs. VREF(+)
(VREF(+) – VREF(–) = 5 V)
–0.1
Figure 9.Typical Digital/Analog
Glitch Impulse
VREF(+) – Volts
INL – LSBs
0.301234567
Figure 5.Typical INL vs. VREF(+)
(VREF(–) = –6 V)
Figure 8.Typical DAC-to-DAC
Matching
VOLTS
VOLTS
–3.105
Figure 11.Settling Time (–)
CODE/1000
INL – LSBs
–0.416468101214
Figure 4.Typical DNL Plot
TEMPERATURE – °C
INL – LSBs
0.7–40+85+25
0.1
Figure 7.Typical INL vs.
Temperature
VOLTS
VOLTS
7.1
Figure 10.Settling Time (+)

Partno	Mfg	Dc	Qty	Available	Descript
AD7834AN	ADI	N/a	2	avai	LC2MOS Quad 14-Bit DAC
AD7834AR	AD	N/a	189	avai	LC2MOS Quad 14-Bit DAC
AD7834BR	AD	N/a	295	avai	LC2MOS Quad 14-Bit DAC
AD7835AS	AD	N/a	19	avai	LC2MOS Quad 14-Bit DAC
AD7835AS	ADI	N/a	75	avai	LC2MOS Quad 14-Bit DAC