AD7828 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7828 ,High Speed , 8-Channel, 8-Bit CMOS ADCfeatures a per-channelconversion rate of 2.5 µs per channel, and the parts have a built-insampling ..
AD7828BQ ,LC2MOS High Speed 4- & 8-Channel 8-Bit ADCs2LC MOS High Speeda4- & 8-Channel 8-Bit ADCsAD7824/AD7828
AD7828BR ,LC2MOS High Speed 4- & 8-Channel 8-Bit ADCsfeatures a per channelconversion rate of 2.5 µ s per channel and the parts have a built-sampling fr ..
AD7828BRS ,LC2MOS High Speed 4- & 8-Channel 8-Bit ADCsspecifications T to T unless otherwise noted.
AD7828CQ ,LC2MOS High Speed 4- & 8-Channel 8-Bit ADCsSPECIFICATIONSnoted. All
AD7828KN ,LC2MOS High Speed 4- & 8-Channel 8-Bit ADCsSpecifications subject to change without notice.–2–REV. DAD7824/AD78281(V = 5 V; V (+) = 5 V; V (–) ..
ADM213AR ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/Receivers0.1 mF, +5 V PoweredaCMOS RS-232 Drivers/ReceiversADM205–ADM211/ADM213TYPICAL OPERATING CIRCUIT
ADM213AR ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/Receivers0.1 mF, +5 V PoweredaCMOS RS-232 Drivers/ReceiversADM205–ADM211/ADM213TYPICAL OPERATING CIRCUIT
ADM213AR-REEL , 0.1 muF, 5 V Powered CMOS RS-232 Drivers/Receivers
ADM213ARS ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION active-high receiver enable control. Two receivers of theThe ADM2xx family of l ..
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ADM213EAR ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/Receiversspecifications and operate at data rates up to 230 kbps.The ADM207E and ADM208E are available in 24 ..

AD7828
High Speed , 8-Channel, 8-Bit CMOS ADC
REV.FLC2MOS High Speed
4- and 8-Channel 8-Bit ADCs
FUNCTIONAL BLOCK DIAGRAM
FEATURES
4 or 8 Analog Input Channels
Built-In Track-and-Hold Function
10 kHz Signal Handling on Each Channel
Fast Microprocessor Interface
Single 5 V Supply
Low Power: 50 mW
Fast Conversion Rate: 2.5 �s/Channel
Tight Error Specification: 1/2 LSB
GENERAL DESCRIPTION
The AD7824 and AD7828 are high speed, multichannel, 8-bit
ADCs with a choice of four (AD7824) or eight (AD7828) multi-
plexed analog inputs. A half-flash conversion technique gives a fast
conversion rate of 2.5 µs per channel, and the parts have a built-in
track-and-hold function capable of digitizing full-scale signals of
10 kHz (157 mV/µs slew rate) on all channels. The AD7824 and
AD7828 operate from a single 5 V supply and have an analog input
range of 0 V to 5 V, using an external 5 V reference.
Microprocessor interfacing of the parts is simple, using standard
Chip Select (CS) and Read (RD) signals to initiate the conversion
and read the data from the three-state data outputs. The half-flash
conversion technique means that there is no need to generate a
clock signal for the ADC. The AD7824 and AD7828 can be
interfaced easily to most popular microprocessors.
The AD7824 and AD7828 are fabricated in an advanced, all
ion-implanted, linear compatible CMOS process (LC2MOS) and
have low power dissipation of 40 mW (typ). The AD7824 is
available in a 0.3" wide, 24-lead “skinny” DIP, while the AD7828
is available in a 0.6" wide, 28-lead DIP and in 28-terminal surface-
mount packages.
PRODUCT HIGHLIGHTS4- or 8-channel input multiplexer gives cost effective,
space-saving multichannel ADC system.Fast conversion rate of 2.5 µs/channel features a per-channel
sampling frequency of 100 kHz for the AD7824 or 50 kHz
for the AD7828.Built-in track-and-hold function allows handling of four or
eight channels up to 10 kHz bandwidth (157 mV/µs slew rate).Tight total unadjusted error spec and channel-to-channel
matching eliminate the need for user trims.Single 5 V supply simplifies system power requirements.Fast, easy-to-use digital interface allows connection to most
popular microprocessors with minimal external components.
No clock signal is required for the ADC.
AD7824/AD7828–SPECIFICATIONS(VDD = 5 V, VREF (+) = 5 V, VREF (–) = GND = O V, unless otherwise
noted. All specifications TMIN to TMAX, unless otherwise noted. Specifications apply to Mode 0.)
ACCURACY
REFERENCE INPUT
ANALOG INPUT
NOTESTemperature ranges are as follows:K, L Versions: 0°C to 70°C
B, C Versions: –40°C to +85°C
T, U Versions: –55°C to +125°CTotal Unadjusted Error includes offset, full-scale and linearity errors.Sample tested at 25°C by Product Assurance to ensure compliance.RDY is an open-drain output.See Typical Performance Characteristics.
Specifications subject to change without notice.
AD7824/AD7828
TIMING CHARACTERISTICS1(VDD = 5 V; VREF(+) = 5 V; VREF(–) = GND = 0 V, unless otherwise noted.)
tAS
tRDY
tCRD
tACC2
tDH
tRD
NOTESSample tested at 25°C to ensure compliance. All input control signals are specified with tRISE = tFALL = 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.CL = 50 pF.Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
a. High-Z to VOH
b. High-Z to VOL
Figure 1.Load Circuits for Data Access Time Test
a. VOH to High-Z
b. VOL to High-Z
Figure 2.Load Circuits for Data Hold Time Test
AD7824/AD7828
Operating Temperature Range
Commercial (K, L Versions) . . . . . . . . . . . . . . 0°C to 70°C
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 300°C
Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . .6 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, 7 V
Digital Input Voltage to GND
(RD, CS, A0, A1, and A2) . . . . . . . . . –0.3 V, VDD + 0.3 V
Digital Output Voltage to GND
(DB0, DB7, RDY, and INT) . . . . . . . –0.3 V, VDD + 0.3 V
VREF (+) to GND . . . . . . . . . . . . . . . . . VREF (–), VDD + 0.3 V
VREF (–) to GND . . . . . . . . . . . . . . . . . . . . . . . .0 V, VREF (+)
Analog Input (Any Channel) . . . . . . . . . .–0.3 V, VDD + 0.3 V
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although AD7824/AD7828 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP/SOIC/SSOP
PLCC
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)AIN2
NC = NO CONNECT
AD7828AIN1NC
DB7DB0
DB6DB1
DB5DB2
DB4DB3
AIN8AIN7AIN6AIN5AIN4AIN3
INT
GND
REF
(–)
REF
(+)
LCCC27123426
AIN2A0
AIN1A1A2
DB0DB7
DB1DB6
DB2DB5
DB3DB4
AIN8AIN7AIN6AIN5AIN4AIN3
ORDERING GUIDE
*Available to /883B processing only. Contact our local sales office for military
data sheet. For U.S. Standard Military Drawing (SMD) see DESC Drawing
#5692-88764.
TPC 1.Conversion Time vs. Temperature
TPC 2.Accuracy vs. VREF [VREF = VREF (+) – VREF (–)]
TPC 3.Signal Noise Ratio vs. Input Frequency
TPC 4.Power Supply Current vs. Temperature
(Not Including Reference Ladder)
TPC 5.Accuracy vs. tP
TPC 6.Output Current vs. Temperature
AD7824/AD7828
OPERATIONAL DIAGRAM
The AD7824 is a 4-channel 8-bit ADC and the AD7828 is an
8-channel 8-bit ADC. Operational diagrams for both of these
devices are shown in Figures 3 and 4. The addition of just a 5 V
reference allows the devices to perform the analog-to-digital function.
Figure 3.AD7824 Operational Diagram
Figure 4.AD7828 Operational Diagram
CIRCUIT INFORMATION
BASIC DESCRIPTION
The AD7824/AD7828 uses a half-flash conversion technique
whereby two 4-bit flash ADCs are used to achieve an 8-bit result.
Each 4-bit flash ADC contains 15 comparators that compare
the unknown input to a reference ladder to get a 4-bit result.
For a full 8-bit reading to be realized, the upper 4-bit flash, the
most significant (MS) flash, performs a conversion to provide
the four most significant data bits. An internal DAC, driven by
the four MSBs, then recreates an analog approximation of the
input voltage. This analog result is subtracted from the input,
and the difference is converted by the lower flash ADC, the least
significant (LS) flash, to provide the four least significant bits of
the output data. The most significant flash ADC also has one
additional comparator to detect overrange on the analog input.
APPLYING THE AD7824/AD7828
REFERENCE AND INPUT
The two reference inputs on the AD7824/AD7828 are fully differ-
ential and define the zero to full-scale input range of the ADC.
As a result, the span of the analog input voltage for all channels
can easily be varied. By reducing the reference span, VREF (+) to
VREF (–), to less than 5 V, the sensitivity of the converter can be
increased (e.g., if VREF = 2 V then 1 LSB = 7.8mV). The input/
reference arrangement also facilitates ratiometric operation.
This reference flexibility also allows the input channel voltage
span to be offset from zero. The voltage at VREF (–) sets the
input level for all channels, which produces a digital output of
all zeroes. Therefore, although the analog inputs are not them-
selves differential, they have nearly differential input capability
in most measurement applications because of the reference
design. Figures 5 to 7 show some of the configurations that are
possible.
Figure 5.Power Supply as Reference
Figure 6.External Reference Using the AD580, Full-Scale
Input is 2.5 V
Figure 7.Input Not Referenced to GND
INPUT CURRENT
Due to the novel conversion techniques employed by the AD7824/
AD7828, the analog input behaves somewhat differently than in
conventional devices. The ADC’s sampled-data comparators
take varying amounts of input current depending on which cycle
the conversion is in.
The equivalent input circuit of the AD7824/AD7828 is shown
in Figure 8. When a conversion starts (CS and RD going low),
all input switches close, and the selected input channel is con-
nected to the most significant and least significant comparators.
Therefore, the analog input is simultaneously connected to
31 input capacitors of 1 pF each.
Figure 8.AD7824/AD7828 Equivalent Input Circuit
The input capacitors must charge to the input voltage through
the on resistance of the analog switches (about 3 kΩ to 6 kΩ). In
addition, about 14 pF of input stray capacitance must be charged.
The analog input for any channel can be modelled as an RC
network, as shown in Figure 9. As RS increases, it takes longer
for the input capacitance to charge.
Figure 9.RC Network Model
The time for which the input comparators track the analog input
is approximately 1 µs at the start of conversion. Because of input
transients on the analog inputs, it is recommended that a source
impedance no greater than 100 Ω be connected to the analog
inputs. The output impedance of an op amp is equal to the open
loop output impedance divided by the loop gain at the frequency of
interest. It is important that the amplifier driving the AD7824/
AD7828 analog inputs have sufficient loop gain at the input signal
frequency as to make the output impedance low.
Suitable op amps for driving the AD7824/AD7828 are the AD544
or AD644.
INHERENT SAMPLE-HOLD
A major benefit of the AD7824’s and AD7828’s analog input
structure is its ability to measure a variety of high speed signals
without the help of an external sample-and-hold. In a conven-
tional SAR type converter, regardless of its speed, the input
must remain stable to at least 1/2 LSB throughout the conversion
process if rated accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally sampled
and held stationary during the conversion. The AD7824/AD7828
input comparators, by nature of their input switching, inherently
accomplish this sample-and-hold function. Although the conver-
sion time for AD7824/AD7828 is 2 µs, the time for which any
selected analog input must be 1/2 LSB stable is much smaller.
The AD7824/AD7828 tracks the selected input channel for
approximately 1 µs after conversion start. The value of the analog
input at that instant (1 µs from conversion start) is the measured
value. This value is then used in the least significant flash to
generate the lower four bits of data.
SINUSOIDAL INPUTS
The AD7824/AD7828 can measure input signals with slew rates
as high as 157 mV/µs to the rated specifications. This means that
the analog input frequency can be up to 10 kHz without the aid
of an external sample-and-hold. Furthermore, the AD7828 can
measure eight 10 kHz signals without a sample-and-hold. The
Nyquist criterion requires that the sampling rate be twice the
input frequency (i.e., 2 × 10 kHz). This requires an ideal anti-
aliasing filter with an infinite roll-off. To ease the problem of
antialiasing filter design, the sampling rate is usually much greater
than the Nyquist criterion. The maximum sampling rate (FMAX)
for the AD7824/AD7828 can be calculated as follows:
tCRD = AD7824/AD7828 Conversion Time
tP = Minimum Delay Between Conversion
This permits a maximum sampling rate of 50 kHz for each of
the eight channels when using the AD7828 and 100 kHz for
each of the four channels when using the AD7824.
AD7824/AD7828
UNIPOLAR OPERATION
The analog input range for any channel of the AD7824/AD7828 is
0 V to 5 V as shown in the unipolar operational diagram of
Figure 10. Figure 11 shows the designed code transitions that
occur midway between successive integer LSB values (i.e., 1/2LSB,
3/2 LSB, 5/2 LSB, FS 3/2 LSBs). The output code is natural
binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV.
Figure 10.AD7824/AD7828 Unipolar 0 V to 5 V Operation
FULL-SCALE
TRANSITION
OUTPUT CODE
1LSB2LSB3LSB
FS – 1LSB0
AIN, INPUT VOLTAGE – LSB
1LSB = FS
256
Figure 11.Ideal Input/Output Transfer Characteristic for
Unipolar 0 V to 5 V Operation
BIPOLAR OPERATION
The circuit of Figure 12 is designed for bipolar operation. An
AD544 op amp conditions the signal input (VIN) so that only
positive voltages appear at AIN1. The closed loop transfer func-
tion of the op amp for the resistor values shown is given below:
The analog input range is ±4 V and the LSB size is 31.25 mV.
The output code is complementary offset binary. The ideal
input/output characteristic is shown in Figure 13.
Figure 12. AD7824/AD7828 Bipolar ±4 V Operation
Figure 13.Ideal Input/Output Transfer Characteristic for
±4 V Operation
TIMING AND CONTROL
The AD7824/AD7828 has two digital inputs for timing and
control. These are Chip Select (CS) and Read (RD). A READ
operation brings CS and RD low, which starts a conversion on
the channel selected by the multiplexer address inputs (see
Table I). There are two modes of operation as outlined by the
timing diagrams of Figures 14 and 15. Mode 0 is designed for
microprocessors that can be driven into a WAIT state. A
READ operation (i.e., CS and RD are taken low) starts a con-
version and data is read when conversion is complete. Mode l
does not require microprocessor WAIT states. A READ operation
initiates a conversion and reads the previous conversion results.
Table I.Truth Table for Input Channel Selection

Partno	Mfg	Dc	Qty	Available	Descript
AD7828	AD	N/a	2	avai	High Speed , 8-Channel, 8-Bit CMOS ADC