AD7823YRM ,2.7 V to 5.5 V, 4.5 us, 8-Bit ADC in 8-Lead microSOIC/DIPspecifications –40C to +125C unless otherwise noted.)REF DDParameter Y Version Unit Test Conditio ..
AD7823YRM-REEL7 ,2.7 V to 5.5 V, 4.5 ms, 8-Bit ADC in 8-Lead microSOIC/DIPSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*SOIC Package, Power Dissip ..
AD7824BQ ,LC2MOS High Speed 4- & 8-Channel 8-Bit ADCsGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD7824 and AD7828 are high-speed, multichannel, 8-bit 1. ..
AD7824CQ ,LC2MOS High Speed 4- & 8-Channel 8-Bit ADCsSpecifications subject to change without notice.–2–REV. DAD7824/AD78281(V = 5 V; V (+) = 5 V; V (–) ..
AD7824KN ,LC2MOS High Speed 4- & 8-Channel 8-Bit ADCsSpecifications subject to change without notice.–2–REV. DAD7824/AD78281(V = 5 V; V (+) = 5 V; V (–) ..
AD7824KR ,LC2MOS High Speed 4- & 8-Channel 8-Bit ADCsspecifications T to T unless otherwise noted.
ADM211EAR-REEL , EMI/EMC-Compliant, ±15 kV ESDProtected, RS-232 Line Drivers/Receivers
ADM211EAR-REEL , EMI/EMC-Compliant, ±15 kV ESDProtected, RS-232 Line Drivers/Receivers
ADM211EARS ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversSPECIFICATIONS(V = +5.0 V 6 10%, C1–C4 = 0.1 mF. All
ADM211EARS. ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversGENERAL DESCRIPTIONNOTES:The ADM2xxE is a family of robust RS-232 and V.28 interface * INTERNAL 40 ..
ADM211EARU ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversSPECIFICATIONS(V = +5.0 V 6 10%, C1–C4 = 0.1 mF. All
ADM211EARU-REEL , EMI/EMC-Compliant, ±15 kV ESDProtected, RS-232 Line Drivers/Receivers
AD7823YN-AD7823YR-AD7823YRM
2.7 V to 5.5 V, 4.5 us, 8-Bit ADC in 8-Lead microSOIC/DIP
REV.B
2.7 V to 5.5 V, 4.5 �s, 8-Bit
ADC in 8-Lead microSOIC/DIP
FUNCTIONAL BLOCK DIAGRAM
DOUT
SCLK
VREFAGNDVDD
VIN+
VIN–
CONVST
FEATURES
8-Bit ADC with 4 �s Conversion Time
Small Footprint 8-Lead microSOIC Package
Specified Over a –40�C to +125�C Temperature Range
Inherent Track-and-Hold Functionality
Operating Supply Range:2.7 V to 5.5 V
Specifications at 2.7 V to 5.5 V and 5 V � 10%
Microcontroller Compatible Serial Interface
Optional Automatic Power-Down
Low Power Operation:
570 �W at 10 kSPS Throughput Rate
2.9 mW at 50 kSPS Throughput Rate
Analog Input Range:0 V to VREF
Reference Input Range:0 V to VDD
“Drop In” Upgrade to 10 Bits Available (AD7810)
APPLICATIONS
Low Power, Hand-Held Portable Applications
Requiring Analog-to-Digital Conversion
with 8-Bit Accuracy, e.g.,
Battery Powered Test Equipment
Battery Powered Communications Systems
GENERAL DESCRIPTIONThe AD7823 is a high speed, low power, 8-bit A/D converter
that operates from a single 2.7 V to 5.5 V supply. The part con-
tains a 4 µs typ successive approximation A/D converter, inherent
track-and-hold functionality (with a pseudo differential input)
and a high speed serial interface that interfaces to most microcon-
trollers. The AD7823 is fully specified over a temperature range
of –40°C to +125°C.
By using a technique that samples the state of the CONVST
(convert start) signal at the end of a conversion, the AD7823
may be used in an automatic power-down mode. When used in
this mode, the AD7823 powers down automatically at the end
of a conversion and “wakes up” at the start of a new conversion.
This feature significantly reduces the power consumption of the
part at lower throughput rates. The AD7823 can also operate in
a high speed mode where the part is not powered down between
conversions. In this high speed mode of operation, the conver-
sion time of the AD7823 is 4 µs typ. The maximum throughput
rate is dependent on the speed of the serial interface of the
microcontroller.
The part is available in a small, 8-lead 0.3" wide, plastic dual-
in-line package (mini-DIP); in an 8-lead, small outline IC
(SOIC); and in an 8-lead microSOIC package.
PRODUCT HIGHLIGHTSComplete, 8-Bit ADC in 8-Lead Package
The AD7823 is an 8-bit 4 µs ADC with inherent track-and-
hold functionality and a high speed serial interface—all in an
8-lead microSOIC package. VREF may be connected to VDD
to eliminate the need for an external reference. The result is
a high speed, low power, space saving ADC solution.Low Power, Single Supply Operation
The AD7823 operates from a single +2.7 V to +5.5 V supply
and typically consumes only 9 mW of power. The power
dissipation can be significantly reduced at lower throughput
rates by using the automatic power-down mode, e.g., at a
throughput rate of 10kSPS the power consumption is only
570µW.Automatic Power-Down
The automatic power-down mode, whereby the AD7823
“powers down” at the end of a conversion and “wakes up”
before the next conversion, means the AD7823 is ideal for
battery powered applications. See Power vs. Throughput
Rate section.Serial Interface
An easy to use, fast serial interface allows connection to most
popular microprocessors with no external circuitry.
AD7823–SPECIFICATIONSDC ACCURACY
ANALOG INPUT
REFERENCE INPUTS
LOGIC OUTPUTS
POWER SUPPLY
NOTES
(GND = 0 V, VREF = +VDD. All specifications –40�C to +125�C unless otherwise noted.)
TIMING CHARACTERISTICS1, 2NOTESSample tested to ensure compliance.See Figures 14, 15 and 16.These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for VDD = 5 V ± 10% and
0.4 V or 2 V for VDD = 3 V ± 10%.Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics, t8, is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(–40�C to +125�C, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Input Voltage to GND
(CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Digital Output Voltage to GND
(DOUT) . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Analog Inputs
(VIN +, VIN –) . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . .+125°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . .+50°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .160°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . .56°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
MicroSOIC Package, Power Dissipation . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .206°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . .44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
ORDERING GUIDE*N = plastic DIP; RM = microSOIC; SO = small outline IC (SOIC).
AD7823
PIN FUNCTION DESCRIPTIONS2VIN+
3VIN–
5VREF
6DOUT
PIN CONFIGURATION
DIP/SOIC/microSOIC
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for an 8-bit converter, this is 50dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7823 it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it will
be a noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7823 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of
different significance. The second order terms are usually
distanced in frequency from the original sine waves while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in dBs.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the idealLSB change between any two adjacent codes in the ADC.
Offset ErrorThis is the deviation of the first code transition (0000...000)
to (0000...001) from the ideal, i.e., AGND + 1 LSB.
Gain ErrorThis is the deviation of the last code transition (1111...110)
to (1111...111) from the ideal (i.e., VREF – 1 LSB) after the
offset error has been adjusted out.
Track/Hold Acquisition TimeTrack/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the VIN+ input of the AD7823. It means that the user must
wait for the duration of the track/hold acquisition time, after the
end of conversion or after a step input change to VIN, before
starting another conversion to ensure that the part operates to
specification.
Typical Performance Characteristics
AD7823
CIRCUIT DESCRIPTION
Converter OperationThe AD7823 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to VDD. Figures
4 and 5 below show simplified schematics of the ADC. Figure 4
shows the ADC during its acquisition phase. SW2 is closed and
SW1 is in Position A; the comparator is held in a balanced
condition; and the sampling capacitor acquires the signal on
VIN+.
Figure 4.ADC Acquisition Phase
When the ADC starts a conversion (see Figure 5) SW2 will
open, and SW1 will move to Position B causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor in order to bring the com-
parator back into a balanced condition. When the comparator
is rebalanced, the conversion is complete. The control logic
generates the ADC output code. Figure 11 shows the ADC
transfer function.
Figure 5.ADC Conversion Phase
TYPICAL CONNECTION DIAGRAMFigure 6 shows a typical connection diagram for the AD7823.
The serial interface is implemented using two wires; the rising
edge of CONVST enables the serial interface—see Serial
Interface section for more details. VREF is connected to a well
decoupled VDD pin to provide an analog input range of 0 V to
VDD. When VDD is first connected, the AD7823 powers up in
a low current mode, i.e., power-down. A rising edge on the
CONVST input will cause the part to power up—see Operating
Modes. If power consumption is of concern, the automatic
power-down at the end of a conversion should be used to im-
prove power performance. See Power vs. Throughput Rate
section of the data sheet.
Figure 6. Typical Connection Diagram
Analog InputFigure 7 shows an equivalent circuit of the analog input struc-
ture of the AD7823. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
The maximum current these diodes can conduct without caus-
ing irreversible damage to the part is 20 mA. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125 Ω. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
Figure 7.Equivalent Analog Input Circuit
The analog input of the AD7823 is made up of a pseudo
differential pair, VIN+ pseudo differential with respect to VIN–.
The signal is applied to VIN+ but in the pseudo differential
scheme the sampling capacitor is connected to VIN– during
conversion—see Figure 8. This input scheme can be used to
remove offsets that exist in a system. For example, if a system
had an offset of 0.5 V, the offset could be applied to VIN– and
the signal applied to VIN+. This has the effect of offsetting the
input span by 0.5 V. It is only possible to offset the input span
when the reference voltage (VREF) is less than VDD – VOFFSET.
Figure 8.Pseudo Differential Input Scheme
