AD7829BRZ ,3V/5V, 8-Bit, 8-Channel, 2 MSPS Data Acquistion Systemapplications.4. Channel SelectionChannel selection is made without the necessity of writing tothe p ..
AD7829BRZ ,3V/5V, 8-Bit, 8-Channel, 2 MSPS Data Acquistion SystemFEATURES FUNCTIONAL BLOCK DIAGRAM8-Bit Half-Flash ADC with 420 ns Conversion TimeVCONVST EOC A0* A1 ..
AD7834AN ,LC2MOS Quad 14-Bit DACSpecifications subject to change without notice–2–REV. AAD7834/AD78351(V = +5 V ± 5%; V = +15 V ± 5 ..
AD7834AR ,LC2MOS Quad 14-Bit DACCHARACTERISTICSsubject to production testing. )Parameter A B S Units Test Conditions/CommentsDYNAMI ..
AD7834BR ,LC2MOS Quad 14-Bit DACGENERAL DESCRIPTIONFour 14-Bit DACs in One Package The AD7834 and AD7835 contain four 14-bit DACs o ..
AD7835AS ,LC2MOS Quad 14-Bit DACSPECIFICATIONSA MIN MAXParameter A B S Units Test Conditions/CommentsACCURACYResolution 14 14 14 Bi ..
ADM2209EARU ,EMI-/EMC-Compliant +-15 kV ESD Protected, Dual RS-232 Port with StandbySPECIFICATIONSMIN MAX1Parameter Min Typ Max Units Test Conditions/CommentsOPERATING CONDITIONSOpera ..
ADM222AN ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTIONEN (ADM242)ADM2xxThe ADM222, ADM232A, ADM242 are a family of high speedSHDN (ADM ..
ADM222AR ,High Speed, +5 V, 0.1 uF CMOS RS-232 Drivers/ReceiversSPECIFICATIONS ifications T to T unless otherwise noted.)MIN MAXParameter Min Typ Max Units Test Co ..
ADM222ARZ , High-Speed, 5 V, 0.1 F CMOS RS-232 Drivers/Receivers
ADM230LAN ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*Thermal Impedance, θJA(T = ..
ADM230LAR ,+5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications120 kB/s Data Rate1 16C1+ +5V TO +10V VCCOn-Board DC-DC Converters 1m F 1m F 1m FVOLT ..
AD7822BRU-REEL7-AD7825BR-REEL7-AD7825BRZ-AD7829BRZ
3V/5V, 8-Bit, 4-Channel, 2 MSPS Data Acquistion System
REV.B
3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel
Sampling ADCs
FUNCTIONAL BLOCK DIAGRAM
CONVST
VREFIN /OUT
EOCCSAGNDVMID
A0* A1* A2*
VIN1
PD*
VDD
DGND
VIN2*
VIN3*
VIN4*
VIN5*
VIN6*
VIN7*
VIN8*
*A0, A1
*A2
*PD
*VIN2 TO VIN4
*VIN4 TO VIN8
AD7825/AD7829
AD7829
AD7822/AD7825
AD7825/AD7829
AD7829
DB0
DB7
FEATURES
8-Bit Half-Flash ADC with 420ns Conversion Time
1, 4 and 8 Single-Ended Analog Input Channels
Available with Input Offset Adjust
On-Chip Track-and-Hold
SNR Performance Given for Input Frequencies Up to
10 MHz
On-Chip Reference (2.5 V)
Automatic Power-Down at the End of Conversion
Wide Operating Supply Range
3 V � 10% and 5 V � 10%
Input Ranges
0 V to 2 V p-p, VDD = 3 V � 10%
0 V to 2.5 V p-p, VDD = 5 V � 10%
Flexible Parallel Interface with EOC Pulse to Allow
Stand-Alone Operation
APPLICATIONS
Data Acquisition Systems, DSP Front Ends
Disk Drives
Mobile Communication Systems, Subsampling
Applications
GENERAL DESCRIPTIONThe AD7822, AD7825, and AD7829 are high speed, 1-, 4-, and
8-channel, microprocessor-compatible, 8-bit analog-to-digital
converters with a maximum throughput of 2 MSPS. The AD7822,
AD7825, and AD7829 contain an on-chip reference of 2.5V
(2% tolerance), a track/hold amplifier, a 420 ns 8-bit half-flash
ADC and a high speed parallel interface. The converters can
operate from a single 3 V ± 10% and 5 V ± 10% supply.
The AD7822, AD7825, and AD7829 combine the convert start
and power-down functions at one pin, i.e., the CONVST pin.
This allows a unique automatic power-down at the end of a
conversion to be implemented. The logic level on the CONVST
pin is sampled after the end of a conversion when an EOC (End
of Conversion) signal goes high, and if it is logic low at that
point, the ADC is powered down. The AD7822 and AD7825
also have a separate power-down pin. (See Operating Modes
section of the data sheet.)
The parallel interface is designed to allow easy interfacing to
microprocessors and DSPs. Using only address decoding logic,
the parts are easily mapped into the microprocessor address
space. The EOC pulse allows the ADCs to be used in a stand-
alone manner. (See Parallel Interface section of the data sheet.)
The AD7822 and AD7825 are available in a 20-/24-lead 0.3"
wide, plastic dual-in-line package (DIP), a 20-/24-lead small out-
line IC (SOIC) and a 20-/24-lead thin shrink small outline package
(TSSOP). The AD7829 is available in a 28-lead 0.6" wide, plastic
dual-in-line package (DIP), a 28-lead small outline IC (SOIC) and
in a 28-lead thin shrink small outline package (TSSOP).
PRODUCT HIGHLIGHTSFast Conversion Time
The AD7822, AD7825, and AD7829 have a conversion time
of 420ns. Faster conversion times maximize the DSP pro-
cessing time in a real-time system.Analog Input Span Adjustment
The VMID pin allows the user to offset the input span. This
feature can reduce the requirements of single-supply op amps
and take into account any system offsets.FPBW (Full Power Bandwidth) of Track-and-Hold
The track-and-hold amplifier has an excellent high-frequency
performance. The AD7822, AD7825, and AD7829 are
capable of converting full-scale input signals up to a fre-
quency of 10MHz. This makes the parts ideally suited to
subsampling applications.Channel Selection
Channel selection is made without the necessity of writing to
the part.
AD7822/AD7825/AD7829–SPECIFICATIONSON-CHIP REFERENCE
LOGIC OUTPUTS
(VDD = 3 V � 10%, VDD = 5 V � 10%, GND = 0 V,
VREF IN/OUT = 2.5 V. All specifications –40�C to +85�C unless otherwise noted.)
POWER REQUIREMENTS
NOTESSee Terminology section of this data sheet.Refer to the Analog Input section for an explanation of the Analog Input(s).
Specifications subject to change without notice.
ORDERING GUIDEFigure 1.Load Circuit for Access Time and Bus
Relinquish Time
AD7822/AD7825/AD7829
AD7822/AD7825/AD7829t10
t13
tPOWER UP
NOTESSample tested to ensure compliance.See Figures 20, 21, and 22.Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V with VDD = 5 V ± 10%, and time required for
an output to cross 0.4V or 2.0V with VDD = 3 V ± 10%.Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
Analog Input Voltage to AGND
VIN1 to VIN8 . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3V
VMID Input Voltage to AGND . . . . . . . –0.3 V to VDD + 0.3V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(VREF IN/OUT = 2.5 V. All specifications –40�C to +85�C unless otherwise noted.)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7822/AD7825/AD7829 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
TIMING CHARACTERISTICS1, 2
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
DIP/SOIC/TSSOP
AD7822/AD7825/AD7829
TERMINOLOGY
Signal-to-(Noise + Distortion) RatioThis is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus, for an 8-bit converter, this is 50dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7822/AD7825/AD7829
it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7822/AD7825/AD7829 are tested using the CCIF stan-
dard where two input frequencies near the top end of the input
bandwidth are used. In this case, the second and third order
terms are of different significance. The second order terms are
usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the intermodula-
tion distortion is as per the THD specification where it is the
ratio of the rms sum of the individual distortion products to the
rms amplitude of the fundamental expressed in dBs.
Channel-to-Channel IsolationChannel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 20kHz
sine wave signal to one input channel and determining how
much that signal is attenuated in each of the other channels.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThe difference between the measured and the ideal 1LSB change
between any two adjacent codes in the ADC.
Offset ErrorThe deviation of the 128th code transition (01111111) to
(10000000) from the ideal, i.e., VMID.
Offset Error MatchThe difference in offset error between any two channels.
Zero-Scale ErrorThe deviation of the first code transition (00000000) to
(00000001) from the ideal, i.e., VMID – 1.25 V + 1 LSB (VDD =
5 V ± 10%), or VMID – 1.0 V + 1 LSB (VDD = 3 V ± 10%).
Full-Scale ErrorThe deviation of the last code transition (11111110) to
(11111111) from the ideal, i.e., VMID + 1.25 V – 1 LSB (VDD =
5 V ± 10%), or VMID + 1.0 V – 1 LSB (VDD = 3 V ± 10%).
Gain ErrorThe deviation of the last code transition (1111...110) to
(1111...111) from the ideal, i.e., VREF – 1 LSB, after the off-
set error has been adjusted out.
Gain Error MatchThe difference in gain error between any two channels.
Track/Hold Acquisition TimeThe time required for the output of the track/hold amplifier to
reach its final value, within ±1/2 LSB, after the point at which
the track/hold returns to track mode. This happens approxi-
mately 120 ns after the falling edge of CONVST.
It also applies to situations where a change in the selected input
channel takes place or where there is a step input change on the
input voltage applied to the selected VIN input of the AD7822/
AD7825/AD7829. It means that the user must wait for the dura-
tion of the track/hold acquisition time after a channel change/step
input change to VIN before starting another conversion, to
ensure that the part operates to specification.
PSR (Power Supply Rejection)Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
CIRCUIT DESCRIPTIONThe AD7822, AD7825, and AD7829 consist of a track-and-hold
amplifier followed by a half-flash analog-to-digital converter.
These devices use a half-flash conversion technique where one
4-bit flash ADC is used to achieve an 8-bit result. The 4-bit
flash ADC contains a sampling capacitor followed by fifteen
comparators that compare the unknown input to a reference
ladder to achieve a 4-bit result. This first flash, i.e., coarse con-
version, provides the 4 MSBs. For a full 8-bit reading to be
realized, a second flash, i.e., a fine conversion, must be per-
Figures 2 and 3 below show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes into
hold mode and holds the analog input for 120 ns. This is the
acquisition phase as shown in Figure 2, when Switch 2 is in Posi-
tion A. At the point when the track-and-hold returns to its track
mode, this signal is sampled by the sampling capacitor as Switch 2
moves into Position B. The first flash occurs at this instant and
is then followed by the second flash. Typically, the first flash is
complete after 100 ns, i.e., at 220 ns, while the end of the second
flash and hence the 8-bit conversion result is available at 330 ns
(minimum). The maximum conversion time is 420 ns. As shown
in Figure 4, the track-and-hold returns to track mode after 120 ns,
and starts the next acquisition before the end of the current
conversion. Figure 6 shows the ADC transfer function.
Figure 2.ADC Acquisition Phase
Figure 4.Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAMFigure 5 shows a typical connection diagram for the AD7822,
AD7825, and AD7829. The AGND and DGND are connected
together at the device for good noise suppression. The parallel
interface is implemented using an 8-bit data bus. The end of
conversion signal (EOC) idles high, the falling edge of CONVST
initiates a conversion and at the end of conversion the falling
edge of EOC is used to initiate an Interrupt Service Routine
(ISR) on a microprocessor. (See Parallel Interface section for
more details.) VREF and VMID are connected to a voltage source
such as the AD780, while VDD is connected to a voltage source
that can vary from 4.5 V to 5.5 V. (See Table I in Analog Input
section.) When VDD is first connected, the AD7822, AD7825, and
AD7829 power up in a low current mode, i.e., power-down, with
the default logic level on the EOC pin on the AD7822 and
AD7825 equal to a low. Ensure the CONVST line is not floating
when VDD is applied, as this could put the AD7822/AD7825/
AD7829 into an unknown state. A suggestion is to tie CONVST
to VDD or DGND through a pull-up or pull-down resistor. A rising
edge on the CONVST pin will cause the AD7829 to fully power up
while a rising edge on the PD pin will cause the AD7822 and
AD7825 to fully power up. For applications where power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power performance.
(See Power-Down Options section of the data sheet.)
AD7822/AD7825/AD7829
ADC TRANSFER FUNCTIONThe output coding of the AD7822, AD7825, and AD7829 is
straight binary. The designed code transitions occur at succes-
sive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size
is = VREF/256 (VDD = 5 V) or the LSB size = (0.8 VREF)/256
(VDD = 3 V). The ideal transfer characteristic for the AD7822,
AD7825, and AD7829 is shown in Figure 6, below.
ADC CODE
(VDD = 5V) VMID – 1.25V
(VDD = 3V) VMID – 1V
VMID + 1.25V – 1LSB
VMID + 1V – 1LSB
ANALOG INPUT VOLTAGEFigure 6.Transfer Characteristic
ANALOG INPUTThe AD7822 has a single input channel and the AD7825 and
AD7829 have four and eight input channels respectively. Each
input channel has an input span of 2.5 V or 2.0 V, depending on
the supply voltage (VDD). This input span is automatically set
up by an on-chip “VDD Detector” circuit. 5 V operation of the
ADCs is detected when VDD exceeds 4.1 V and 3 V operation is
detected when VDD falls below 3.8 V. This circuit also possesses
a degree of glitch rejection; for example, a glitch from 5.5 V to
2.7 V up to 60 ns wide will not trip the VDD detector.
The VMID pin is used to center this input span anywhere in the
range AGND to VDD. If no input voltage is applied to VMID, the
default input range is AGND to 2.0 V (VDD = 3 V ± 10%) i.e.,
centered about 1.0 V, or AGND to 2.5 V (VDD = 5 V ± 10%)
i.e., centered about 1.25V. When using the default input range,
the VMID pin can be left unconnected or, in some cases, it can be
decoupled to AGND with a 0.1�F capacitor.
If, however, an external VMID is applied, the analog input range
will be from VMID – 1.0 V to VMID + 1.0 V (VDD = 3 V ± 10%),
or from VMID – 1.25 V to VMID + 1.25 V (VDD = 5 V ± 10%).
The range of values of VMID that can be applied depends on the
value of VDD. For VDD = 3 V ± 10%, the range of values that
can be applied to VMID is from 1.0 V to VDD – 1.0 V and is 1.25 V
to VDD – 1.25 V when VDD= 5 V ± 10%. Table I shows the rel-
evant ranges of VMID and the input span for various values of
VDD. Figure 7 illustrates the input signal range available with
various values of VMID.
Table I.Figure 7.Analog Input Span Variation with VMID
VMID may be used to remove offsets in a system by applying the
offset to the VMID pin as shown in Figure 8, or it may be used to
accommodate bipolar signals by applying VMID to a level-shifting
circuit before VIN, as shown in Figure 9. When VMID is being
driven by an external source, the source may be directly tied to
the level-shifting circuitry (see Figure 9); however, if the internal
VMID, i.e., the default value, is being used as an output, it must
be buffered before applying it to the level-shifting circuitry, as
the VMID pin has an impedance of approximately 6kΩ (see
Figure 10).
Figure 8.Removing Offsets Using VMID
Figure 9.Accommodating Bipolar Signals Using
External VMID
Figure 10.Accommodating Bipolar Signals Using
Internal VMID
NOTE: Although there is a VREF pin from which a voltage refer-
ence of 2.5 V may be sourced, or to which an external reference
may be applied, this does not provide an option of varying
the value of the voltage reference. As stated in the specifications
for the AD7822, AD7825, and AD7829, the input voltage range
at this pin is 2.5 V ± 2%.
Analog Input StructureFigure 11 shows an equivalent circuit of the analog input structure
of the AD7822, AD7825, and the AD7829. The two diodes, D1
and D2, provide ESD protection for the analog inputs. Care
must be taken to ensure that the analog input signal never exceeds
the supply rails by more than 200 mV. This will cause these
diodes to become forward biased and start conducting current into
the substrate. 20 mA is the maximum current these diodes can
conduct without causing irreversible damage to the part. How-
ever, it is worth noting that a small amount of current (1 mA)
being conducted into the substrate due to an over voltage on an
unselected channel, can cause inaccurate conversions on a
selected channel. The capacitor C2 in Figure 11 is typically
about 4 pF and can be primarily attributed to pin capacitance.
The resistor, R1, is a lumped component made up of the on
resistance of several components, including that of the multi-
plexer and the track and hold. This resistor is typically about
310 Ω. The capacitor C1 is the track-and-hold capacitor and
has a capacitance of 0.5 pF. Switch 1 is the track-and-hold switch,
while Switch 2 is that of the sampling capacitor as shown in
Figures 2 and 3.
Figure 11.Equivalent Analog Input Circuit
When in track phase, Switch 1 is closed and Switch 2 is in
Position A; when in hold mode, Switch 1 opens while Switch
2 remains in Position A. The track-and-hold remains in hold
mode for 120 ns—see Circuit Description—after which it returns
to track mode and the ADC enters its conversion phase. At this
point, Switch 1 opens and Switch 2 moves to Position B. At the
end of the conversion, Switch 2 moves back to Position A.
Analog Input SelectionOn power-up, the default VIN selection is VIN1. When returning
to normal operation from power-down, the VIN selected will be
the same one that was selected prior to power-down being initiated.
Table II below shows the multiplexer address corresponding to
each analog input from VIN1 to VIN4(8) for the AD7825 or AD7829.
Table II.Channel selection on the AD7825 and AD7829 is made without
the necessity of a write operation. The address of the next channel
to be converted is latched at the start of the current read operation,
i.e., on the falling edge of RD while CS is low, as shown in Figure
12. This allows for improved throughput rates in “channel
hopping” applications.
AD7822/AD7825/AD7829Figure 12.Channel Hopping Timing
There is a minimum time delay between the falling edge of RD
and the next falling edge of the CONVST signal, t13. This is the
minimum acquisition time required of the track-and-hold in
order to maintain 8-bit performance. Figure 13 shows the typical
performance of the AD7825 when channel hopping for various
acquisition times. These results were obtained using an external
reference and internal VMID while channel hopping between
VIN1 and VIN4 with 0 V on Channel 4 and 0.5 V on Channel 1.
Figure 13.Effective Number of Bits vs. Acquisition Time
for the AD7825
The on-chip track-and-hold can accommodate input frequen-
cies to 10 MHz, making the AD7822, AD7825, and AD7829
ideal for subsampling applications. When the AD7825 is con-
verting a 10 MHz input signal at a sampling rate of 2 MSPS,
the effective number of bits typically remains above seven,
corresponding to a signal-to-noise ratio of 42 dBs as shown
in Figure 14.
Figure 14.SNR vs. Input Frequency on the AD7825
POWER-UP TIMESThe AD7822/AD7825/AD7829 have a 1 µs power-up time when
using an external reference and a 25 µs power-up time when using
the on-chip reference. When VDD is first connected, the AD7822,
AD7825, and AD7829 are in a low current mode of operation.
Ensure that the CONVST line is not floating when VDD is applied,
as if there is a glitch on CONVST while VDD is rising, the part will
attempt to power up before VDD has fully settled and could enter
an unknown state. In order to carry out a conversion, the AD7822,
AD7825, and AD7829 must first be powered up. The AD7829 is
powered up by a rising edge on the CONVST pin and a conversion
is initiated on the falling edge of CONVST. Figure 15 shows how
to power up the AD7829 when VDD is first connected or after the
AD7829 has been powered down using the CONVST pin when
using either the on-chip, or an external, reference. When using
an external reference, the falling edge of CONVST may occur
before the required power-up time has elapsed; however, the
conversion will not be initiated on the falling edge of CONVST but
rather at the moment when the part has completely powered up,
i.e., after 1 µs. If the falling edge of CONVST occurs after the required
power-up time has elapsed, then it is upon this falling edge that a
conversion is initiated. When using the on-chip reference, it is nec-
essary to wait the required power-up time of approximately 25 µs
before initiating a conversion; i.e., a falling edge on CONVST
may not occur before the required power-up time has elapsed,
when VDD is first connected or after the AD7829 has been powered
down using the CONVST pin as shown in Figure 15.
