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AD7821KN-AD7821KP-AD7821KR
LC2MOS High Speed, mP-Compatible 8-Bit ADC with Track/Hold Function
REV.A
LC2MOS High Speed, mP-Compatible
8-Bit ADC with Track/Hold Function
FUNCTIONAL BLOCK DIAGRAMFEATURES
Fast Conversion Time: 660 ns max
100 kHz Track-and-Hold Function
1 MHz Sample Rate
Unipolar and Bipolar Input Ranges
Ratiometric Reference Inputs
No External Clock
Extended Temperature Range Operation
Skinny 20-Pin DlPs, SOIC and 20-Terminal
Surface Mount Packages
GENERAL DESCRIPTIONThe AD7821 is a high speed, 8-bit, sampling, analog-to-digital
converter that offers improved performance over the popular
AD7820. It offers a conversion time of 660 ns (vs. 1.36 μs for
the AD7820) and 100 kHz signal bandwidth (vs. 6.4 kHz). The
sampling instant is better defined and occurs on the falling edge
of WR or RD. The provision of a VSS pin (Pin 19) allows the
part to operate from ±5 V supplies and to digitize bipolar input
signals. Alternatively, for unipolar inputs, the VSS pin can be
grounded and the AD7821 will operate from a single +5 V sup-
ply, like the AD7820.
The AD7821 has a built-in track-and-hold function capable of
digitizing full-scale signals up to 100 kHz max. It also uses a
half-flash conversion technique that eliminates the need to gen-
erate a CLK signal for the ADC.
The AD7821 is designed with standard microprocessor control
signals (CS, RD, WR, RDY, INT) and latched, three-state data
outputs capable of interfacing to high speed data buses. An
overflow output (OFL) is also provided for cascading devices to
achieve higher resolution.
The AD7821 is fabricated in Linear-Compatible CMOS
(LC2MOS), an advanced, mixed technology process combining
precision bipolar circuits with low power CMOS logic. The part
features a low power dissipation of 50 mW.
PRODUCT HIGHLIGHTS1. Fast Conversion Time
The half-flash conversion technique, coupled with fabrication
on Analog Devices’ LC2MOS process, enables a very fast con-
version time. The conversion time for the WR-RD mode is
660 ns, with 700 ns for the RD mode.
2. Built-In Track-and-Hold
This allows input signals with slew rates up to 1.6 V/μs to be
converted to 8-bits without an external track-and-hold. This
corresponds to a 5 V peak-to-peak, 100 kHz sine wave signal.
3. Total Unadjusted Error
The AD7821 features an excellent total unadjusted error fig-
ure of less than ±1 LSB over the full operating temperature
range.
4. Unipolar/Bipolar Input Ranges
The AD7821 is specified for single supply (+5 V) operation
with a unipolar full-scale range of 0 to +5 V, and for dual sup-
ply (±5 V) operation with a bipolar input range of ±2.5 V.
Typical performance characteristics are given for other input
ranges.
5. Dynamic Specifications for DSP Users
In addition to the traditional ADC specifications, the
AD7821 is specified for ac parameters, including signal-to-
noise ratio, distortion and slew rate.
AD7821–SPECIFICATIONS
VDD = +5 V 6 5%, GND = 0 V. Unipolar Input Range: VSS = GND, VREF(+) = 5 V,
VREF(–) = GND. Bipolar Input Range: VSS = –5 V 6 5%, VREF(+) = 2.5 V,
VREF(–) = –2.5 V. These test conditions apply unless otherwise stated. All specifications TMIN to TMAX unless otherwise noted. Specifications
apply for RD Mode (Pin 7 = 0 V).UNIPOLAR INPUT RANGE
BIPOLAR INPUT RANGE
ANALOG INPUT
LOGIC INPUTS
LOGIC OUTPUTS
POWER SUPPLY
NOTES
1Temperature Ranges are as follows: K Version = –40°C to +85°C; B Version = –40°C to +85°C; T Version = –55°C to +125°C.
21 LSB = 19.53 mV for both the unipolar (0 V to +5 V) and bipolar (–2.5 V to +2.5 V) input ranges.
3See Terminology.
4Sample tested at +25°C to ensure compliance.
5See Typical Performance Characteristics.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1(VDD = +5 V ± 5%, VSS = 0 V or –5 V ± 5%; Unipolar or Bipolar Input Range)tCSH
tRDY
tINTH
tDH
tRD
tRI
tINTL
tREAD2
tIHWR
tID
NOTESSample tested at +25°C to ensure compliance. All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2CL = 50 pF.Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test CircuitsHigh Z to VOHb.High Z to VOL
Figure 1.Load Circuits for Data Access Time Test
ORDERING GUIDENOTESTo order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.
Power Supply Current vs. Tempera-
ture (Not Including Reference Ladder)
Accuracy vs. tP
tINTL, Internal Time Delay vs.
Temperature
Accuracy vs. tWR
Accuracy vs. VREF
[VREF = VREF(+) – VREF(–)]
Output Current vs. Temperature
Conversion Time (RD Mode) vs.
Temperature
Accuracy vs. tRD
Effective Number of Bits vs. Input
Signal (±2.5 V) Frequency
AD7821
PIN FUNCTION DESCRIPTIONCIRCUIT INFORMATION
BASIC DESCRIPTION
The AD7821 uses a half flash conversion technique (see Func-
tional Block Diagram), whereby two 4-bit flash ADCs are used
to achieve an 8-bit result. Each 4-bit flash ADC contains 15
comparators, which compare an unknown input voltage to the
reference ladder, to achieve a 4-bit result. The MS (most signifi-
cant) flash ADC converts an unknown analog input voltage
(VIN) to provide the 4 MS data bits. An internal DAC, driven by
the 4 MS data bits, then recreates an analog approximation of
the input voltage. The DAC output voltage is subtracted from
the analog input, and the difference is converted by the LS
OPERATING SEQUENCEThe AD7821 has two operating modes. The RD mode allows a
conversion to be started and data to be read with a single, ex-
tended, READ operation (i.e., CS and RD are taken low). The
conversion process is timed out by internal one-shots. The WR-
RD mode uses WR to start a conversion and RD to read the
data and allows the conversion timing to be externally con-
trolled. The operating sequence for the WR-RD mode is shown
in Figure 3.
Figure 3.Operating Sequence (WR-RD Mode)
A conversion is initiated and the analog input signal (VIN)
sampled on the falling edge of WR (falling edge of RD, RD
mode). A setup time (tP, delay time between conversions) of
350 ns is required prior to this falling edge. See Digital Interface
section for more details. When WR is low, the internal MS
(most significant) ADC compares the sampled analog input with
the reference ladder to provide the 4 MS data bits. A minimum
of 250 ns is required for this comparison. On the rising edge of
WR, the MS data result is latched internally and the LS (least
significant) conversion begins, to yield the 4 LS data bits. INT
goes low typically 380 ns after the rising edge of WR. This indi-
cates the LS conversion is complete and that both the LS and
MS data results are latched into the output buffer. RD going
low then enables the output data. If a faster conversion time is
required, the RD line can be brought low 250 ns after WR goes
high. This latches both the LS and MS data bits and outputs the
conversion result on DB0–DB7.
REFERENCE AND INPUTThe VREF(–) and VREF(+) reference inputs on the AD7821 are
fully differential and define the zero and full-scale input range of
the ADC. The transfer characteristic of the part is defined by
the integer value of the following expression:
Data (LSBs)=256VIN−VREF(−)
VREF(+)−VREF(−)+0.5
As a result, the analog input (VIN) Of the device can easily be set
up to provide both unipolar and bipolar operation. The data
output code for unipolar and bipolar operation is Natural Binary
and Offset Binary, respectively.
The span of the analog input voltage can easily be varied.
By reducing the reference span, VREF(+) – VREF(–), to less than
5 V the sensitivity of the converter can be increased (i.e., if
VREF = 2 V then 1 LSB = 7.8 mV). The reference flexibility also
allows the input span for unipolar operation to be offset from
zero (VREF(–) > GND). Additionally, the input/reference ar-
rangement facilitates ratiometric operation.
