AD781AN-AD781JN Fast Delivery |IC PHOENIX CO.,LIMITED

AD781JN ,Complete 700 ns Sample-and-Hold AmplifierSPECIFICATIONSAD781J AD781A AD781SParameter Min Typ Max Min Typ Max Min Typ Max UnitsTOTAL HARMONIC ..
AD7820KN ,LC2MOS HIGH-SPEED uP-COMPATIBLE 8-BIT ADC WITH TRACK/HOLD FUNCTIONFEATURES Fast Conversion Time: 1.36pa max BuiIt-ln Trattk-artd-Hoid Function No Missed Cod ..
AD7820KP ,LC2MOS HIGH-SPEED uP-COMPATIBLE 8-BIT ADC WITH TRACK/HOLD FUNCTIONGENERAL DESCRIPTION The AD7820 is a high speed, microprocessor-compatible 8-bit analog-to-digit ..
AD7820KR ,LC2MOS HIGH-SPEED uP-COMPATIBLE 8-BIT ADC WITH TRACK/HOLD FUNCTIONGENERAL DESCRIPTION The AD7820 is a high speed, microprocessor-compatible 8-bit analog-to-digit ..
AD7820LN ,LC2MOS HIGH-SPEED uP-COMPATIBLE 8-BIT ADC WITH TRACK/HOLD FUNCTIONfeatures a low maximum power dissipation of 75mW. It is available in 20-pin DIPs, SOICs and in 20- ..
AD7820LP ,LC2MOS HIGH-SPEED uP-COMPATIBLE 8-BIT ADC WITH TRACK/HOLD FUNCTIONfeatures a low maximum power dissipation of 75mW. It is available in 20-pin DIPs, SOICs and in 20- ..
ADM208AR ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION active-high receiver enable control. Two receivers of theThe ADM2xx family of l ..
ADM208AR ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications T to T unless otherwise noted.)MIN MAXParameter Min Typ Max Units Test Conditions/Co ..
ADM208AR-REEL , 0.1 muF, 5 V Powered CMOS RS-232 Drivers/Receivers
ADM208ARS ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversSPECIFICATIONS211, 213); V = +5 V 6 5% (ADM205);CCV+ = +9 V to +13.2 V (ADM209); C1–C4 = 0.1 mF Cer ..
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AD781AN-AD781JN
Complete 700 ns Sample-and-Hold Amplifier
FUNCTIONAL BLOCK DIAGRAM
REV.AComplete 700 ns
Sample-and-Hold Amplifier
PRODUCT DESCRIPTION
The AD781 is a high speed monolithic sample-and-hold
amplifier (SHA). The AD781 guarantees a maximum
acquisition time of 700 ns to 0.01% over temperature. The
AD781 is specified and tested for hold mode total harmonic
distortion and hold mode signal-to-noise and distortion. The
AD781 is configured as a unity gain amplifier and uses a
self-correcting architecture that minimizes hold mode errors and
insures accuracy over temperature. The AD781 is self-contained
and requires no external components or adjustments.
The low power dissipation, 8-pin mini-DIP package and
completeness make the AD781 ideal for highly compact board
layouts. The AD781 will acquire a full-scale input in less than
700 ns and retain the held value with a droop rate of 0.01 μV/μs.
Excellent linearity and hold mode dc and dynamic performance
make the AD781 ideal for 12- and 14-bit high speed analog-
to-digital converters.
The AD781 is manufactured on Analog Devices’ BiMOS
process which merges high performance, low noise bipolar
circuitry with low power CMOS to provide an accurate, high
speed, low power SHA.
The AD781 is specified for three temperature ranges. The J
grade device is specified for operation from 0°C to +70°C, the A
grade from –40°C to +85°C and the S grade from –55°C to
+125°C. The J and A grades are available in 8-pin plastic DIP
packages. The S grade is available in an 8-pin cerdip package.
*. Patent No. 4,962,325.
PRODUCT HIGHLIGHTSFast acquisition time (700 ns), low aperture jitter (75 ps) and
fully specified hold mode distortion make the AD781 an
ideal SHA for sampling systems.Low droop (0.01 μV/μs) and internally compensated hold
mode error results in superior system accuracy.Low power (95 mW typical), complete functionality and
small size make the AD781 an ideal choice for a variety of
high performance, low power applications.The AD781 requires no external components or adjustments.Excellent choice as a front-end SHA for high speed analog-
to-digital converters such as the AD671, AD7586, AD674B,
AD774B, AD7572 and AD7672.Fully specified and tested hold mode distortion guarantees
the performance of the SHA in sampled data systems.The AD781 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD781/883B data sheet for detailed
specifications.
FEATURES
Acquisition Time to 0.01%: 700 ns Maximum
Low Power Dissipation: 95 mW
Low Droop Rate: 0.01 mV/ms
Fully Specified and Tested Hold Mode Distortion
Total Harmonic Distortion: –80 dB Maximum
Aperture Jitter: 75 ps Maximum
Internal Hold Capacitor
Self-Correcting Architecture
8-Pin Mini Cerdip and Plastic Package
MIL-STD-883 Compliant Versions Available
AD781–SPECIFICATIONS
DC SPECIFICATIONS
HOLD CHARACTERISTICS
ACCURACY CHARACTERISTICS
INPUT CHARACTERISTICS
DIGITAL CHARACTERISTICS
TEMPERATURE RANGE
NOTESpecified and tested over an input range of ±5 V.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed although only those shown in boldface are tested.
(TMIN to TMAX, VCC = +12 V 6 10%, VEE = –12 V 6 10%, CL = 20 pF, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under “Absolute Maximum Ratings” may cause per-
manent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.
HOLD MODE AC SPECIFICATIONS
NOTEFIN amplitude = 0 dB and FSAMPLE = 500 kHz unless otherwise indicated.
Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed although only those shown in boldface are tested.
Specifications subject to change without notice.
(TMIN to TMAX, VCC = +12 V 6 10%, VEE = –12 V 6 10%, CL = 20 pF,
unless otherwise noted)1
AD781
PIN CONFIGURATION
NOTESFor details on grade and package offerings screened in accordance with
MIL-STD-883, refer to the Analog Devices Military Products Databook or
current AD781/883B data sheet.N = Plastic DIP; Q = Cerdip.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts.
AD781
Power Supply Rejection Ratio vs.
Frequency
INPUT VOLTAGE – V
BIAS CURRENT – nA
Bias Current vs. Input Voltage
TEMPERATURE – °C
DROOP RATE –
Droop Rate vs. Temperature,
VIN = 0 V
TEMPERATURE – °C
SUPPLY CURRENT – mA
Supply Current vs. Temperature
INPUT STEP – V
ACQUISITION TIME – ns
Acquisition Time (to 0.01%) vs.
Input Step Size
1001M
100k10k
FREQUENCY – Hz
EFFECTIVE APERTURE DELAY – ns
Effective Aperture Delay vs.
Frequency
DEFINITIONS OF SPECIFICATIONS
Acquisition Time—The length of time that the SHA must
remain in the sample mode in order to acquire a full-scale input
step to a given level of accuracy.
Small Signal Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 100 mV p-p sine wave.
Full Power Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 10 V p-p sine wave.
Effective Aperture Delay—The difference between the switch
delay and the analog delay of the SHA channel. A negative
number indicates that the analog portion of the overall delay is
greater than the switch portion. This effective delay represents
the point in time, relative to the hold command, that the input
signal will be sampled.
Aperture Jitter—The variations in aperture delay for
successive samples. Aperture jitter puts an upper limit on the
maximum frequency that can be accurately sampled.
Hold Settling Time—The time required for the output to
settle to within a specified level of accuracy of its final held value
after the hold command has been given.
Droop Rate—The drift in output voltage while in the hold
mode.
Feedthrough—The attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
Hold Mode Offset—The difference between the input signal
and the held output. This offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of 0 V.
Tracking Mode Offset—The difference between the input and
output signals when the SHA is in the track mode.
Nonlinearity--The deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of –5 V and +5 V.
Gain Error—Deviation from a gain of +1 on the transfer
function of input vs. held output.
Power Supply Rejection Ratio—A measure of change in the
held output voltage for a specified change in the positive or
negative supply.
Sampled DC Uncertainty—The internal rms SHA noise that
is sampled onto the hold capacitor.
Hold Mode Noise—The rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
Total Output Noise—The total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms
summation of the sampled dc uncertainty and the hold mode
noise.
Output Drive Current—The maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.5 mV.
Signal-To-Noise and Distortion (S/N+D) Ratio—S/N+D is
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Total Harmonic Distortion (THD)—THD is the ratio of the
rms sum of the first six harmonic components to the rms value
of the measured input signal and is expressed as a percentage or
in decibels.
Intermodulation Distortion (IMD)—With inputs consisting
of sine waves at two frequencies, fa and fb, any device with
nonlinearities will create distortion products, of order (m+n), at
sum and difference frequency of mfa±nfb, where m, n = 0, 1, 2,
3.... Intermodulation terms are those for which m or n is not
equal to zero. For example, the second order terms are (fa+fb)
and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),
(fa+2fb) and (fa–2fb). The IMD products are expressed as the
decibel ratio of the rms sum of the measured input signals to the
rms sum of the distortion terms. The two signals are of equal
amplitude, and peak value of their sums is –0.5 dB from full
scale. The IMD products are normalized to a 0 dB input signal.
FUNCTIONAL DESCRIPTION
The AD781 is a complete sample-and hold amplifier that
provides high speed sampling to 12-bit accuracy in less than
700 ns.
The AD781 is completely self-contained, including an on-chip
hold capacitor, and requires no external components or
adjustments to perform the sampling function. Both input and
output are treated as a single-ended signal, referred to common.
The AD781 utilizes a proprietary circuit design which includes a
self-correcting architecture. This sample-and-hold circuit
corrects for internal errors after the hold command has been
given, by compensating for amplifier gain and offset errors, and
charge injection errors. Due to the nature of the design, the
SHA output in the sample mode is not intended to provide an
accurate representation of the input. However, in hold mode,
the internal circuitry is reconfigured to produce an accurately
held version of the input signal. Below is a block diagram of the
AD781.
AD781
DYNAMIC PERFORMANCE
The AD781 is compatible with 12-bit A-to-D converters in
terms of both accuracy and speed. The fast acquisition time, fast
hold settling time and good output drive capability allow the
AD781 to be used with high speed, high resolution A-to-D
converters like the AD674 and AD7672. The AD781’s fast
acquisition time provides high throughput rates for multichannel
data acquisition systems. Typically, the sample and hold can
acquire a 10 V step in less than 600 ns. Figure 1 shows the
settling accuracy as a function of acquisition time.
ACQUISITION TIME – ns
V ACQUISITION ACCURACY – %
OUT
Figure 1.VOUT Settling vs. Acquisition Time
The hold settling determines the required time, after the hold
command is given, for the output to settle to its final specified
accuracy. The typical settling behavior of the AD781 is shown
in Figure 2. The settling time of the AD781 is sufficiently fast to
allow the SHA, in most cases, to directly drive an A-to-D
converter without the need for an added “start convert” delay.
Figure 2.Typical AD781 Hold Mode
HOLD MODE OFFSET
The dc accuracy of the AD781 is determined primarily by the
hold mode offset. The hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. The hold mode offset arises
from a voltage error introduced onto the hold capacitor by
charge injection of the internal switches. The nominal hold
mode offset is specified for a 0 V input condition. Over the
input range of –5 V to +5 V, the AD781 is also characterized for
an effective gain error and nonlinearity of the held value, as
Figure 3.
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accom-
plished through the A-to-D itself or by an external amplifier
with offset nulling capability (e.g., AD711). The offset will
change less than 0.5 mV over the specified temperature range.
SUPPLY DECOUPLING AND GROUNDING
CONSIDERATIONS
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from exces-
sive high frequency noise (ripple). The supply connection to the
AD781 should also be capable of delivering transient currents to
the device. To achieve the specified accuracy and dynamic per-
formance, decoupling capacitors must be placed directly at both
the positive and negative supply pins to common. Ceramic type
0.1 μF capacitors should be connected from VCC and VEE to
common.
The AD781 does not provide separate analog and digital ground
leads as is the case with most A-to-D converters. The common
pin is the single ground terminal for the device. It is the refer-
ence point for the sampled input voltage and the held output
voltage and also the digital ground return path. The common
pin should be connected to the reference (analog) ground of the

Partno	Mfg	Dc	Qty	Available	Descript
AD781AN	AD	N/a	3	avai	Complete 700 ns Sample-and-Hold Amplifier
AD781JN	AD	N/a	87	avai	Complete 700 ns Sample-and-Hold Amplifier