AD7813YR ,+2.7 V to +5.5 V, 400 kSPS 8-/10-Bit Sampling ADCCHARACTERISTICSParameter V = 3 V 10% V = 5 V 10% Unit Conditions/CommentsDD DDt 11 µ s (max) Po ..
AD7813YR ,+2.7 V to +5.5 V, 400 kSPS 8-/10-Bit Sampling ADCSPECIFICATIONSParameter Y Version Unit Test Conditions/CommentsDYNAMIC PERFORMANCE f = 30 kHz, f = ..
AD7814ARM-REEL7 , 10-Bit Digital Temperature Sensor in 6-Lead SOT-23
AD7814ARMZ , 10-Bit Digital Temperature Sensor in 6-Lead SOT-23
AD7814ART ,10-Bit Digital Temperature Sensor in 6-Lead SOT-23CHARACTERISTICSA MIN MAX DDParameter Limit Units Commentst 0 ns min CS to SCLK Setup Time1t 50 ns m ..
AD7814ART ,10-Bit Digital Temperature Sensor in 6-Lead SOT-23SPECIFICATIONSA MIN MAX DDParameter Min Typ Max Units Test Conditions/CommentsTEMPERATURE SENSOR AN ..
ADM206AN ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION active-high receiver enable control. Two receivers of theThe ADM2xx family of l ..
ADM206AR ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications T to T unless otherwise noted.)MIN MAXParameter Min Typ Max Units Test Conditions/Co ..
ADM206ARS ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/Receiversapplications where ±12 V is not available. The ADM205,All members of the ADM2xx family, except the ..
ADM206EAR ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversGENERAL DESCRIPTIONNOTES:The ADM2xxE is a family of robust RS-232 and V.28 interface * INTERNAL 40 ..
ADM206EAR ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/Receiversspecifications T to T unless otherwise noted.)CC MIN MAXParameter Min Typ Max Units Test Conditions ..
ADM207AN ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversAPPLICATIONS8 R1 9 R1R1OUT INComputers5 R2 4 R2R2 INPeripherals OUTRS-232TTL/CMOS26 R3 27 R3Modems ..
AD7813YR
+2.7 V to +5.5 V, 400 kSPS 8-/10-Bit Sampling ADC
REV. B
+2.7 V to +5.5 V, 400 kSPS
8-/10-Bit Sampling ADC
FUNCTIONAL BLOCK DIAGRAM
VIN
CONVST
VDDAGNDVREF
DB7
BUSYCSRD
DB0
FEATURES
8-/10-Bit ADC with 2.3 �s Conversion Time
On-Chip Track and Hold
Operating Supply Range: +2.7 V to +5.5 V
Specifications at 2.7 V–3.6 V and 5 V � 10%
8-Bit Parallel Interface
8-Bit + 2-Bit Read
Power Performance
Normal Operation
10.5 mW, VDD = 3 V
Automatic Power-Down
34.6 �W @ 1 kSPS, VDD = 3 V
Analog Input Range: 0 V to VREF
Reference Input Range: 1.2 V to VDD
GENERAL DESCRIPTIONThe AD7813 is a high-speed, microprocessor-compatible,
8-/10-bit analog-to-digital converter with a maximum through-
put of 400 kSPS. The converter operates off a single +2.7 V to
+5.5 V supply and contains a 2.3 µs successive approximation
A/D converter, track/hold circuitry, on-chip clock oscillator and
8-bit wide parallel interface. The parallel interface is designed to
allow easy interfacing to microprocessors and DSPs. The 10-bit
conversion result is read by carrying out two 8-bit read opera-
tions. The first read operation accesses the 8 MSBs of the ADC
conversion result and the second read accesses the 2 LSBs.
Using only address decoding logic the AD7813 is easily mapped
into the microprocessor address space.
When used in its power-down mode, the AD7813 automatically
powers down at the end of a conversion and powers up at the
start of a new conversion. This feature significantly reduces the
power consumption of the part at lower throughput rates. The
AD7813 can also operate in a high speed mode where the part is
not powered down between conversions. In this mode of opera-
tion the part is capable of providing 400 kSPS throughput.
The part is available in a small, 16-lead, 0.3" wide, plastic dual-
in-line package (DIP), in a 16-lead, 0.15" wide, narrow body
small outline IC (SOIC) and in a 16-lead thin shrink small
outline package (TSSOP).
PRODUCT HIGHLIGHTSLow Power, Single Supply Operation
The AD7813 operates from a single +2.7 V to +5.5 V sup-
ply and typically consumes only 10.5 mW of power. The
power dissipation can be significantly reduced at lower
throughput rates by using the automatic power-down mode.Automatic Power-Down
The automatic power-down mode, whereby the AD7813
goes into power-down mode at the end of a conversion and
powers up before the next conversion, means the AD7813
is ideal for battery powered applications; e.g., 34.6 µW
@ 1 kSPS. (See Power vs. Throughput Rate section.)Parallel Interface
An easy to use 8-bit-wide parallel interface allows interfacing
to most popular microprocessors and DSPs with minimal
external circuitry.Dynamic Specifications for DSP Users
In addition to the traditional ADC specifications, the AD7813
is specified for ac parameters, including signal-to-noise ratio
and distortion.
AD7813–SPECIFICATIONS1(GND = 0 V, VREF = +VDD = 3 V � 10% to 5 V � 10%. All specifications –40�C to
+105�C unless otherwise noted.)DC ACCURACY
REFERENCE INPUTS
LOGIC OUTPUTS
POWER SUPPLY
NOTESSee Terminology section.
ORDERING GUIDE
TIMING CHARACTERISTICS1, 2tPOWER-UP
NOTESSample tested to ensure compliance.See Figures 12, 13 and 14.These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for VDD = 5 V ± 10% and
0.4 V or 2 V for VDD = 3 V ± 10%.Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
(–40�C to +105�C, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Input Voltage to DGND
(CONVST, RD, CS) . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Digital Output Voltage to DGND
(BUSY, DB0–DB7) . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Analog Input . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . .+105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . .+260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .115°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≥4 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Figure 1.Load Circuit for Digital Output Timing
Specifications
AD7813
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
DIP/SOIC
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for an 10-bit converter, this is 62dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7813 it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7813 is tested using the CCIF standard, where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of differ-
ent significance. The second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the idealLSB change between any two adjacent codes in the ADC.
Offset ErrorThis is the deviation of the first code transition (0000...000)
to (0000...001) from the ideal, i.e., AGND + 1 LSB.
Offset Error MatchThis is the difference in Offset Error between any two channels.
Gain ErrorThis is the deviation of the last code transition (1111...110)
to (1111...111) from the ideal, i.e., VREF – 1 LSB, after the
offset error has been adjusted out.
Gain Error MatchThis is the difference in Gain Error between any two channels.
Track/Hold Acquisition TimeTrack/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected VIN input of the AD7813. It means that the user
must wait for the duration of the track/hold acquisition time
after the end of conversion, or after a step input change to VIN,
before starting another conversion, to ensure that the part
operates to specification.
AD7813
CIRCUIT DESCRIPTION
Converter OperationThe AD7813 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to VDD. Fig-
ures 2 and 3 below show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on VIN+.
Figure 2.ADC Track Phase
When the ADC starts a conversion (see Figure 3), SW2 will
open and SW1 will move to Position B, causing the comparator
to become unbalanced. The Control Logic and the Charge
Redistribution DAC are used to add and subtract fixed amounts
of charge from the sampling capacitor so as to bring the com-
parator back into a balanced condition. When the comparator is
rebalanced the conversion is complete. The Control Logic gen-
erates the ADC output code. Figure 7 shows the ADC transfer
function.
Figure 3.ADC Conversion Phase
TYPICAL CONNECTION DIAGRAMFigure 4 shows a typical connection diagram for the AD7813. The
parallel interface is implemented using an 8-bit data bus, the
falling edge of CONVST brings the BUSY signal high, and at
the end of conversion the falling edge of BUSY is used to ini-
tiate an Interrupt Service Routine (ISR) on a microprocessor—
see Parallel Interface section for more details. VREF is connected
to a well decoupled VDD pin to provide an analog input range of
0 V to VDD. When VDD is first connected the AD7813 powers
up in a low current mode, i.e., power-down. A rising edge on an
internal CONVST input will cause the part to power up—see
Power-Up Times. If power consumption is of concern, the
automatic power-down at the end of a conversion should be
used to improve power performance. See Power vs. Throughput
Rate section of the data sheet.
Figure 4.Typical Connection Diagram
Analog InputFigure 5 shows an equivalent circuit of the analog input struc-
ture of the AD7813. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
The maximum current these diodes can conduct without caus-
ing irreversible damage to the part is 20 mA. The capacitor C2,
in Figure 5, is typically about 4 pF and can be primarily attrib-
uted to pin capacitance. The resistor R1 is a lumped component
made up of the on resistance of a multiplexer and a switch. This
resistor is typically about 125 Ω. The capacitor C1 is the ADC
sampling capacitor and has a capacitance of 3.5 pF.
Figure 5.Equivalent Analog Input Circuit
DC Acquisition TimeThe ADC starts a new acquisition phase at the end of a conver-
sion and ends on the falling edge of the CONVST signal. At the
end of a conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 100 ns.
The analog signal on VIN is also being acquired during this settling
time; therefore, the minimum acquisition time needed is ap-
proximately 100 ns.
Figure 6 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R2 repre-
sents the source impedance of a buffer amplifier or resistive
network, R1 is an internal multiplexer resistance and C1 is the
sampling capacitor.
