AD7811YRU-REEL ,10-Bit, 4-Channel, 350 kSPS, Serial A/D ConverterCHARACTERISTICSDD REF DDParameter Y Version Unit Conditions/Commentst 1.5 µ s (max) Power-Up Time o ..
AD7811YRU-REEL7 ,10-Bit, 4-Channel, 350 kSPS, Serial A/D ConverterGENERAL DESCRIPTIONPower vs. Throughput.The AD7811 and AD7812 are high speed, low power, 10-bit2. 4 ..
AD7812YR ,+2.7 V to +5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCsSPECIFICATIONS Parameter Y Version Units Test Conditions/CommentsDYNAMIC PERFORMANCE f = 30 kHz Any ..
AD7812YRU ,+2.7 V to +5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCsGENERAL DESCRIPTIONThroughput.The AD7811 and AD7812 are high speed, low power, 10-bit2. 4-/8-Channe ..
AD7812YRU-REEL7 ,10-Bit, 8-Channel, 350 kSPS, Serial A/D ConverterSPECIFICATIONS Parameter Y Version Unit Test Conditions/CommentsDYNAMIC PERFORMANCE f = 30 kHz Any ..
AD7812YRUZ ,10-Bit, 8-Channel, 350 kSPS, Serial A/D Converterfeatures a software convertThe AD7811 has Four Single-Ended Inputs thatstart and a software power-d ..
ADM202JRWZ , High-Speed, 5 V, 0.1 F CMOS RS-232 Driver/Receivers
ADM203JN ,High Speed, +5 V, 0.1 uF CMOS RS-232 Driver/ReceiversSpecifications6.3V6.3VDOUBLERC1– V+ 23Two Drivers and Two ReceiversOn-Board DC-DC ConvertersC2+4 +1 ..
ADM205AN ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversFEATURES0.1 mF to 10 mF Capacitors+5V INPUT120 kB/s Data Rate2 Receivers Active in Shutdown (ADM213 ..
ADM206AN ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION active-high receiver enable control. Two receivers of theThe ADM2xx family of l ..
ADM206AR ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications T to T unless otherwise noted.)MIN MAXParameter Min Typ Max Units Test Conditions/Co ..
ADM206ARS ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/Receiversapplications where ±12 V is not available. The ADM205,All members of the ADM2xx family, except the ..
AD7811YRU-REEL-AD7811YRU-REEL7-AD7812YRU-REEL7-AD7812YRUZ-AD7812YRUZ.
10-Bit, 4-Channel, 350 kSPS, Serial A/D Converter
2.7 V to 5.5 V, 350 kSPS, 10-Bit
4-/8-Channel Sampling ADCs
FEATURES
10-Bit ADC with 2.3 �s Conversion Time
The AD7811 has Four Single-Ended Inputs that
Can Be Configured as Three Pseudo Differential
Inputs with Respect to a Common, or as Two Inde-
pendent Pseudo Differential Channels
The AD7812 has Eight Single-Ended Inputs that Can
Be Configured as Seven Pseudo Differential Inputs
with Respect to a Common, or as Four Independent
Pseudo Differential Channels
Onboard Track and Hold
Onboard Reference 2.5 V � 2.5%
Operating Supply Range: 2.7 V to 5.5 V
Specifications at 2.7 V–3.6 V and 5 V � 10%
DSP-/Microcontroller-Compatible Serial Interface
High Speed Sampling and Automatic Power-Down Modes
Package Address Pin on the AD7811 and AD7812 Allows
Sharing of the Serial Bus in Multipackage Applications
Input Signal Range: 0 V to VREF
Reference Input Range: 1.2 V to VDD
GENERAL DESCRIPTIONThe AD7811 and AD7812 are high speed, low power, 10-bit
A/D converters that operate from a single 2.7 V to 5.5 V supply.
The devices contain a 2.3 µs successive approximation A/D
converter, an on-chip track/hold amplifier, a 2.5 V on-chip refer-
ence and a high speed serial interface that is compatible with the
serial interfaces of most DSPs (Digital Signal Processors) and
microcontrollers. The user also has the option of using an exter-
nal reference by connecting it to the VREF pin and setting the
EXTREF bit in the control register. The VREF pin may be tied
to VDD. At slower throughput rates the power-down mode may
be used to automatically power down between conversions.
The control registers of the AD7811 and AD7812 allow the
input channels to be configured as single-ended or pseudo
differential. The control register also features a software convert
start and a software power-down. Two of these devices can
share the same serial bus and may be individually addressed in
a multipackage application by hardwiring the device address pin.
The AD7811 is available in a small, 16-lead 0.3" wide, plastic
dual-in-line package (mini-DIP), in a 16-lead 0.15" wide, Small
Outline IC (SOIC) and in a 16-lead, Thin Shrink Small Out-
line Package (TSSOP). The AD7812 is available in a small,
20-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a
20-lead, Small Outline IC (SOIC) and in a 20-lead, Thin Shrink
Small Outline Package (TSSOP).
PRODUCT HIGHLIGHTSLow Power, Single Supply Operation
Both the AD7811 and AD7812 operate from a single 2.7 V
to 5.5 V supply and typically consume only 10 mW of power.
The power dissipation can be significantly reduced at
lower throughput rates by using the automatic power-
down mode e.g., 315 µW @ 10 kSPS, VDD = 3 V—see
Power vs. Throughput.4-/8-Channel, 10-Bit ADC
The AD7811 and AD7812 have four and eight single-ended
input channels respectively. These inputs can be configured
as pseudo differential inputs by using the Control Register.On-chip 2.5 V (±2.5%) reference circuit that is powered
down when using an external reference.Hardware and Software Control
The AD7811 and AD7812 provide for both hardware and
software control of Convert Start and Power-Down.
FUNCTIONAL BLOCK DIAGRAMSREV.B
CONVST
AGND
REFINVDD
DOUT
DGND
VIN1
VIN2
VIN3
VIN4
DIN
RFS
TFS
SCLK
CREF
AGNDREFINVDD
DOUT
DGND
DIN
RFS
TFS
SCLK
CREF
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
CONVST
AD7811/AD7812–SPECIFICATIONS
(VDD = 2.7 V to 3.6 V, VDD = 5 V � 10%, GND = 0 V, VREF = VDD
[EXT]. All specifications –40�C to +105�C unless otherwise noted.)
AD7811/AD7812NOTESSee Terminology.Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2NOTESSample tested to ensure compliance.See Figures 16, 17 and 18.These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for VDD = 5 V ± 10% and
0.4 V or 2 V for VDD = 3 V ± 10%.Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t11, quoted in the Timing Characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = 2.7 V to 5.5 V, VREF = VDD [EXT] unless otherwise noted)Figure 1.Load Circuit for Digital Output Timing Specifications
AD7811/AD7812
ABSOLUTE MAXIMUM RATINGS*VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Input Voltage to DGND (CONVST, SCLK, RFS, TFS,
DIN, A0) . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Digital Output Voltage to DGND (DOUT)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Analog Inputs
VIN1–VIN4 (AD7811) . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VIN1–VIN8 (AD7812) . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . .260°C
ORDERING GUIDESOIC Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .115°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7811/AD7812 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
DIP/SOIC/TSSOP
AD7811/AD7812
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distor-
tion) ratio for an ideal N-bit converter with a sine wave input
is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 10-bit converter, this is 62dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7811 and AD7812
it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it will
be a noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7811 and AD7812 are tested using the CCIF standard
where two input frequencies near the top end of the input
bandwidth are used. In this case, the second and third order
terms are of different significance. The second order terms are
usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the inter-
modulation distortion is as per the THD specification where it is
the ratio of the rms sum of the individual distortion products to
the rms amplitude of the fundamental expressed in dBs.
Channel-to-Channel IsolationChannel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 20kHz sine wave signal to all nonselected input channels
and determining how much that signal is attenuated in the selected
channel. The figure given is the worst case across all four or
eight channels for the AD7811 and AD7812 respectively.
Relative AccuracyRelative accuracy, or endpoint nonlinearity, is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the idealLSB change between any two adjacent codes in the ADC.
Offset ErrorThis is the deviation of the first code transition (0000...000)
to (0000...001) from the ideal, i.e., AGND + 1 LSB.
Offset Error MatchThis is the difference in Offset Error between any two channels.
Gain ErrorThis is the deviation of the last code transition (1111...110)
to (1111...111) from the ideal, i.e., VREF – 1 LSB, after the
offset error has been adjusted out.
Gain Error MatchThis is the difference in Gain Error between any two channels.
Track/Hold Acquisition TimeTrack/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected VIN input of the AD7811 or AD7812. It means
that the user must wait for the duration of the track/hold acquisi-
tion time after the end of conversion or after a channel change/
step input change to VIN before starting another conversion, to
ensure that the part operates to specification.
Control Register (AD7811)The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7811 receives a falling
edge on its TFS pin. The AD7811 will maintain the same configuration until a new control byte is written to the part. The control
register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is
being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros;
therefore, when the supplies are connected, the AD7811 is powered down by default.
Control Register AD7811 *This is a don’t care bit.This is the package address bit. It is used in conjunction with the package address pin to allow two AD7811s to
share the same serial bus. The AD7811 can also share the same serial bus with the AD7812. When a control word
is written to the control register of the AD7811 the control word is ignored if the package address bit in the con-
trol byte does not match how the package address pin is hardwired. Only the serial port of the device that received
the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus on the
next serial read. When the part powers up this bit is set to 0.
PD1, PD0These bits allow the AD7811 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and
PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the
power-down mode when the AD7811 enters a power-down at the end of a conversion. There are two power-down
modes—Full Power-Down and Partial Power-Down. See Power-Down Options section of this data sheet.
VIN4/AGNDThe DIF/SGL bit in the control register must be set to 0 to use this option otherwise this bit is ignored. Setting
VIN4/AGND to 0 configures the analog inputs of the AD7811 as four single-ended analog inputs referenced to
analog ground (AGND). By setting this bit to 1 the input channels VIN1 to VIN3 are configured as three pseudo-
differential channels with respect to VIN4—see Table I.
DIF/SGLThis bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0
the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to
VIN4 as explained above. Setting this bit to 1 configures the analog input channels as two pseudo differential pairs
VIN1/VIN2 and VIN3/VIN4—see Table I.
CH1, CH0These bits are used in conjunction with VIN4/AGND and DIF/SGL to select an analog input channel. The table
shows how the various channel selections are made—see Table I.
CONVSTSetting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control
register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion
initiated in the same serial write. The bit is reset after the end of a conversion.
EXTREFThis bit must be set to a logic one if the user wishes to use an external reference or use VDD as the reference.
When the external reference is selected the on chip reference circuitry powers down.
AD7811/AD7812
Control Register (AD7812)The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7812 receives a falling
edge on its TFS pin. The AD7812 will maintain the same configuration until a new control byte is written to the part. The control
register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is
being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros;
therefore, when the supplies are connected, the AD7812 is powered down by default.
Control Register AD7812This is the package address bit. It is used in conjunction with the package address pin to allow two AD7812s to
share the same serial bus. The AD7812 can also share the same serial bus with the AD7811. When a control word
is written to the control register of the AD7812 the control word is ignored if the package address bit in the con-
trol byte does not match how the package address pin is hardwired. Only the serial port of the device which
received the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus
on the next serial read. When the part powers up this bit is set to 0.
PD1, PD0These bits allow the AD7812 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and
PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the
power-down mode when the AD7812 enters a power-down at the end of a conversion. There are two power-down
modes—Full Power-Down and Partial Power-Down. See Power-Down section of this data sheet.
VIN8/AGNDThe DIF/SGL bit in the control register must be set to 0 in order to use this option otherwise this bit is ignored.
Setting VIN8/AGND to 0 configures the analog inputs of the AD7812 as eight single-ended analog inputs
referenced to analog ground (AGND). By setting this bit to 1 the input channels VIN1 to VIN7 are configured
as seven pseudo differential channels with respect to VIN8—see Table II.
DIF/SGLThis bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0
the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to
VIN8 as explained above. Setting this bit to 1 configures the analog input channels as four pseudo differential pairs
VIN1/VIN2, VIN3/VIN4, VIN5/VIN6 and VIN7/VIN8—see Table II.
CH2, CH1, CH0These bits are used in conjunction with VIN8/AGND and DIF/SGL to select an analog input channel. Table II
shows how the various channel selections are made.
CONVSTSetting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control
register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initi-
ated in the same write operation. The bit is reset after the end of a conversion.
EXTREFThis bit must be set to a logic one if the user wishes to use an external reference or use VDD as the reference.
When the external reference is selected the on-chip reference circuitry powers down and the current consumption
is reduced by about 1 mA.
Table I.AD7811 Channel Configurations
Table II.AD7812 Channel Configurations
AD7811/AD7812
CIRCUIT DESCRIPTION
Converter OperationThe AD7811 and AD7812 are successive approximation analog-
to-digital converters based around a charge redistribution DAC.
The ADCs can convert analog input signals in the range 0 V to
VDD. Figures 2 and 3 show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in position A, the comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on VIN.
VIN
VDD/3
COMPARATOR
PHASE
SW1
AGNDFigure 2.ADC Acquisition Phase
When the ADC starts a conversion, see Figure 3, SW2 will
open and SW1 will move to position B causing the comparator
to become unbalanced. The Control Logic and the Charge
Redistribution DAC are used to add and subtract fixed amounts
of charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The Control Logic generates
the ADC output code. Figure 10 shows the ADC transfer
function.
VIN
VDD/3
CONVERSION
PHASE
SW1
SAMPLING
CAPACITOR
AGNDFigure 3. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAMFigure 4 shows a typical connection diagram for the AD7811/
AD7812. The AGND and DGND are connected together at
the device for good noise suppression. The serial interface is
implemented using three wires with RFS/TFS connected to
CONVST see Serial Interface section for more details. VREF is
connected to a well decoupled VDD pin to provide an analog
input range of 0 V to VDD. If the AD7811 or AD7812 is not
sharing a serial bus with another AD7811 or AD7812 then A0
(package address pin) should be hardwired low. The default
power up value of the package address bit in the control register
is 0. For applications where power consumption is of concern,
the automatic power down at the end of a conversion should be
used to improve power performance. See Power-Down Options
section of the data sheet.
Figure 4. Typical Connection Diagram
Analog InputFigure 5 shows an equivalent circuit of the analog input struc-
ture of the AD7811 and AD7812. The two diodes D1 and D2
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 200 mV. This will cause these diodes
to become forward biased and start conducting current into
the substrate. 20 mA is the maximum current these diodes can
conduct without causing irreversible damage to the part. How-
ever, it is worth noting that a small amount of current (1 mA)
being conducted into the substrate due to an overvoltage on an
unselected channel can cause inaccurate conversions on a
selected channel. The capacitor C2 in Figure 5 is typically about
4 pF and can primarily be attributed to pin capacitance. The
resistor R1 is a lumped component made up of the on resistance
of a multiplexer and a switch. This resistor is typically about
125 Ω. The capacitor C1 is the ADC sampling capacitor and
has a capacitance of 3.5 pF.
Figure 5.Equivalent Analog Input Circuit
The analog inputs on the AD7811 and AD7812 can be config-
ured as single ended with respect to analog ground (AGND),
as pseudo differential with respect to a common, and also as
pseudo differential pairs—see Control Register section.
