AD7810YN-AD7810YR Fast Delivery |IC PHOENIX CO.,LIMITED

AD7810YR ,2.7 V to 5.5 V, 2 us, 10-Bit ADC in 8-Lead microSOIC/DIPGENERAL DESCRIPTIONPRODUCT HIGHLIGHTSThe AD7810 is a high speed, low power, 10-bit A/D con-1. Compl ..
AD7810YR-REEL ,2.7 V to 5.5 V, 2 ms, 10-Bit ADC in 8-Lead microSOIC/DIPSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*SOIC Package, Power Dissip ..
AD7811YR ,+2.7 V to +5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCsCHARACTERISTICSDD REF DDParameter Y Version Units Conditions/Commentst 1 m s (max) Power-Up Time of ..
AD7811YRU ,+2.7 V to +5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCsfeatures a software convertThe AD7811 has Four Single-Ended Inputs thatstart and a software power-d ..
AD7811YRU-REEL ,10-Bit, 4-Channel, 350 kSPS, Serial A/D ConverterCHARACTERISTICSDD REF DDParameter Y Version Unit Conditions/Commentst 1.5 µ s (max) Power-Up Time o ..
AD7811YRU-REEL7 ,10-Bit, 4-Channel, 350 kSPS, Serial A/D ConverterGENERAL DESCRIPTIONPower vs. Throughput.The AD7811 and AD7812 are high speed, low power, 10-bit2. 4 ..
ADM202JRW ,High Speed, +5 V, 0.1 uF CMOS RS-232 Driver/Receiversspecifications. Fast driver slew rates permit operation up toDO NOT MAKE8 C1+11CONNECTIONS TO C2+12 ..
ADM202JRWZ , High-Speed, 5 V, 0.1 F CMOS RS-232 Driver/Receivers
ADM203JN ,High Speed, +5 V, 0.1 uF CMOS RS-232 Driver/ReceiversSpecifications6.3V6.3VDOUBLERC1– V+ 23Two Drivers and Two ReceiversOn-Board DC-DC ConvertersC2+4 +1 ..
ADM205AN ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversFEATURES0.1 mF to 10 mF Capacitors+5V INPUT120 kB/s Data Rate2 Receivers Active in Shutdown (ADM213 ..
ADM206AN ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversGENERAL DESCRIPTION active-high receiver enable control. Two receivers of theThe ADM2xx family of l ..
ADM206AR ,0.1 uF, +5 V Powered CMOS RS-232 Drivers/ReceiversSpecifications T to T unless otherwise noted.)MIN MAXParameter Min Typ Max Units Test Conditions/Co ..

AD7810YN-AD7810YR
2.7 V to 5.5 V, 2 us, 10-Bit ADC in 8-Lead microSOIC/DIP
REV.A
2.7 V to 5.5 V, 2 ms, 10-Bit
ADC in 8-Lead microSOIC/DIP
FUNCTIONAL BLOCK DIAGRAM
FEATURES
10-Bit ADC with 2 ms Conversion Time
Small Footprint 8-Lead microSOIC Package
Specified Over a –408C to +1058C Temperature Range
Inherent Track-and-Hold Functionality
Operating Supply Range:2.7 V to 5.5 V
Specifications at 2.7 V to 5.5 V
Microcontroller-Compatible Serial Interface
Optional Automatic Power-Down
at End of Conversion
Low Power Operation
270 mW at 10 kSPS Throughput Rate
2.7 mW at 100 kSPS Throughput Rate
Analog Input Range:0 V to VREF
Reference Input Range:0 V to VDD
APPLICATIONS
Low Power, Hand-Held Portable Applications that
Require Analog-to-Digital Conversion with 10-Bit
Accuracy; e.g., Battery Powered Test Equipment,
Battery Powered Communications Systems
GENERAL DESCRIPTION
The AD7810 is a high speed, low power, 10-bit A/D con-
verter that operates from a single 2.7 V to 5.5 V supply. The
part contains a 2 ms successive approximation A/D converter,
with inherent track/hold functionality, a pseudo differential
input and a high speed serial interface that interfaces to most
microcontrollers. The AD7810 is fully specified over a tem-
perature range of –40°C to +105°C.
By using a technique that samples the state of the CONVST
(convert start) signal at the end of a conversion, the AD7810
may be used in an automatic power-down mode. When used in
this mode, the AD7810 automatically powers down at the end
of a conversion and “wakes up” at the start of a new conversion.
This feature significantly reduces the power consumption of the
part at lower throughput rates. The AD7810 can also operate in
a high speed mode where the part is not powered down between
conversions. In this high speed mode of operation, the conver-
sion time of the AD7810 is 2 ms. The maximum throughput rate
is dependent on the speed of the serial interface of the micro-
controller.
The part is available in a small 8-lead, 0.3" wide, plastic dual-
in-line package (mini-DIP); in an 8-lead, small outline IC
(SOIC); and in an 8-lead microSOIC package.
PRODUCT HIGHLIGHTSComplete, 10-Bit ADC in 8-Lead Package
The AD7810 is a 10-bit 2 ms ADC with inherent track/hold
functionality and a high speed serial interface—all in an
8-lead microSOIC package. VREF may be connected to VDD
to eliminate the need for an external reference. The result is
a high speed, low power, space saving ADC solution.Low Power, Single Supply Operation
The AD7810 operates from a single +2.7 V to +5.5 V supply
and typically consumes only 9 mW of power while convert-
ing. The power dissipation can be significantly reduced at
lower throughput rates by using the automatic power-down
mode, e.g., at a throughput rate of 10 kSPS the power
consumption is only 270 mW.Automatic Power-Down
The automatic power-down mode, whereby the AD7810
powers down at the end of a conversion and “wakes up”
before the next conversion, means the AD7810 is ideal for
battery powered applications. See Power vs. Throughput
Rate section.Serial Interface
An easy to use, fast serial interface allows connection to most
popular microprocessors with no external circuitry.
AD7810–SPECIFICATIONS
DC ACCURACY
ANALOG INPUT
REFERENCE INPUTS
LOGIC OUTPUTS
POWER SUPPLY
NOTESSee Terminology section.Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
(GND = 0 V, VREF = +VDD. All specifications –408C to +1058C unless otherwise noted.)
Timing Characteristics1, 2
NOTES
1Sample tested to ensure compliance.
2See Figures 14, 15 and 16.
3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for VDD = 5 V – 10% and
0.4 V or 2 V for VDD = 3 V – 10%.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(–408C to +1058C, VREF = +VDD, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND
(CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Digital Output Voltage to GND
(DOUT) . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Analog Inputs
(VIN+, VIN–) . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . +125°C/WJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . +50°C/W
Lead Temperature Soldering (10 sec) . . . . . . . . . . +260°C
IOH
200mA
+1.6V
OUTPUT
PIN
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/WJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/WJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
AD7810
PIN FUNCTION DESCRIPTIONS
2VIN+
3VIN–
5VREF
6DOUT
PIN CONFIGURATION
DIP/SOIC
CONVST
VIN+
VIN–
GND
VDD
SCLK
DOUT
VREF
THROUGHPUT – kSPS
POWER – mW
0.14050
Figure 2.Power vs. Throughput
Typical Performance Characteristics
FREQUENCY BINS
dBs
–15
Figure 3.AD7810 SNR
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 10-bit converter, this is 62␣dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7810 it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V62 are the rms amplitudes of the second through
the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms values of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the sec-
ond order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa –
2fb).
The AD7810 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of differ-
ent significance. The second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the idealLSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (0000...000)
to (0000...001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
This is the deviation of the last code transition (1111...110)
to (1111...111) from the ideal (i.e., VREF – 1 LSB) after the
offset error has been adjusted out.
Track/Hold Acquisition Time
Track/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the VIN+ input of the AD7810. It means that the user must
wait for the duration of the track/hold acquisition time, after the
end of conversion or after a step input change to VIN+, before
starting another conversion to ensure that the part operates to
specification.
AD7810
CIRCUIT DESCRIPTION
Converter Operation
The AD7810 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to VDD. Fig-
ures 4 and 5 below show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A; the comparator is held in a
balanced condition; and the sampling capacitor acquires the
signal on VIN+.
VDD/3
VIN+
SAMPLING
VIN–
Figure 4.ADC Acquisition Phase
When the ADC starts a conversion (see Figure 5), SW2 will
open and SW1 will move to Position B, causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. Figure 11 shows the ADC transfer function.
VDD/3
VIN+
SAMPLING
PHASE
VIN–
Figure 5.ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7810. The
serial interface is implemented using two wires; the rising edge
of CONVST enables the serial interface—see Serial Interface
section for more details. VREF is connected to a well decoupled
VDD pin to provide an analog input range of 0 V to VDD. When
VDD is first connected, the AD7810 powers up in a low current
mode, i.e., power-down. A rising edge on the CONVST input
will cause the part to power up—see Operating Modes. If power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power perfor-
mance. See Power vs. Throughput Rate section of the data sheet.
SUPPLY
+2.7V TO +5.5V
0V TO VREF
INPUT
Figure 6.Typical Connection Diagram
Analog Input
Figure 7 shows an equivalent circuit of the analog input struc-
ture of the AD7810. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
The maximum current these diodes can conduct without caus-
ing irreversible damage to the part is 20 mA. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125 W. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
VDD
VIN+
VDD/3
ACQUISITION PHASE – SWITCH CLOSED
Figure 7.Equivalent Analog Input Circuit
The analog input of the AD7810 is made up of a pseudo differ-
ential pair. VIN+ pseudo differential with respect to VIN–. The
signal is applied to VIN+, but in the pseudo differential scheme
the sampling capacitor is connected to VIN– during conversion
(see Figure 8). This input scheme can be used to remove offsets
that exist in a system. For example, if a system had an offset of
0.5 V, the offset could be applied to VIN– and the signal applied
to VIN+. This has the effect of offsetting the input span by 0.5 V.
It is only possible to offset the input span when the reference
voltage (VREF) is less than VDD – VOFFSET.
VDD/3
VIN+
VIN–
VIN(+)
VOFFSET
Figure 8.Pseudo Differential Input Scheme

Partno	Mfg	Dc	Qty	Available	Descript
AD7810YN	AD	N/a	42	avai	2.7 V to 5.5 V, 2 us, 10-Bit ADC in 8-Lead microSOIC/DIP
AD7810YR	AD	N/a	150	avai	2.7 V to 5.5 V, 2 us, 10-Bit ADC in 8-Lead microSOIC/DIP