AD7804BN-AD7804BR-AD7805BN-AD7805BR-AD7805BRS-AD7805CR-AD7808BR-AD7809BST Fast Delivery |IC PHOENIX CO.,LIMITED

AD7805BR ,+3.3 V to +5 V Quad/Octal 10-Bit DACsspecifications T to T unless otherwise noted.)L L MIN MAX1 1Parameter B Grade C Grade Units Comment ..
AD7805BRS ,+3.3 V to +5 V Quad/Octal 10-Bit DACsspecifications T to T unless otherwise noted.)L L MIN MAX1 1Parameter B Grade C Grade Units Comment ..
AD7805CR ,+3.3 V to +5 V Quad/Octal 10-Bit DACsCHARACTERISTICS3Output Voltage Range V – 15/16 · V V – 15/16 · V V Twos Complement CodingBIAS BIAS ..
AD7808BR ,+3.3 V to +5 V Quad/Octal 10-Bit DACsspecifications T to T unless otherwise noted.)L L MIN MAX1Parameter B Grade Units CommentsSTATIC PE ..
AD7809BST ,+3.3 V to +5 V Quad/Octal 10-Bit DACsFeatures Channels Controlled Main DAC Sub DACDATA DACCHANNEL BHardware Clear All ÏÏREGISTER REGISTE ..
AD780AN ,2.5 V/3.0 V High Precision ReferenceSpecifications subject to change without notice.–2– REV. BAD780ABSOLUTE MAXIMUM RATINGS* DIE LAYOUT ..
ADM202EAN ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversGENERAL DESCRIPTIONNOTE*INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUTThe ADM202E and ADM1181 ..
ADM202EARN ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversspecificationsCCADM202E/ADM1181A–
ADM202EARN-REEL7 , EMI/EMC-Compliant, -15 kV, ESD-Protected RS-232 Line Drivers/Receivers
ADM202EARNZ-REEL , EMI/EMC-Compliant, -15 kV, ESD-Protected RS-232 Line Drivers/Receivers
ADM202EARNZ-REEL , EMI/EMC-Compliant, -15 kV, ESD-Protected RS-232 Line Drivers/Receivers
ADM202EARU ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversCHARACTERISTICSMaximum Data Rate 230 kbps R = 3 kΩ to 7 kΩ, C = 50 pF to 2500 pFL LReceiver Propaga ..

AD7804BN-AD7804BR-AD7805BN-AD7805BR-AD7805BRS-AD7805CR-AD7808BR-AD7809BST
+3.3 V to +5 V Quad/Octal 10-Bit DACs
GENERAL DESCRIPTION
The AD7804/AD7808 are quad/octal 10-bit digital-to-analog
converters, with serial load capabilities, while the AD7805/AD7809
are quad/octal 10-bit digital-to-analog converters with parallel
load capabilities. These parts operate from a +3.3 V to +5 V10%) power supply and incorporates an on-chip reference.
These DACs provide output signals in the form of VBIAS – VSWING.
VSWING is derived internally from VBIAS. On-chip control registers
include a system control register and channel control registers.
The system control register has control over all DACs in the
package. The channel control registers allow individual control
of DACs. The complete transfer function of each individual
DAC can be shifted around the VBIAS point using an on-chip
Sub DAC. All DACs contain double buffered data inputs,
which allow all analog outputs to be simultaneously updated
using the asynchronous LDAC input.
NOTESPower-down function powers down all internal circuitry including the reference.Standby functions power down all circuitry except for the reference.
FUNCTIONAL BLOCK DIAGRAMS
VOUTD
VOUTC
VOUTB
VOUTA
REFIN
REFOUT
LDACCLR
AVDDDVDDAGNDDGND
CLKIN
FSIN
COMP
SDIN
VOUTG*
VOUTE*
VOUTH*
VOUTF*
PD**
**ONLY AD7804 SHOWN FOR CLARITY
**SHOWS ADDITIONAL CHANNELS ON THE AD7808
**PIN ON THE AD7808 ONLY
VOUTD
VOUTC
VOUTB
VOUTA
REFIN
REFOUT
LDACCLR
AVDDDVDDAGNDDGND
COMP
MODEA0A1DB9DB2DB1DB0
VOUTG*
VOUTH*
PD**
**ONLY AD7805 SHOWN FOR CLARITY
**SHOWS ADDITIONAL CHANNELS ON THE AD7809
**PIN ON THE AD7809 ONLY
A2**
VOUTE*
VOUTF*
*Patent pending.REV.A+3.3 V to +5 V Quad/Octal 10-Bit DACs
FEATURES
Four 10-Bit DACs in One Package
Serial and Parallel Loading Facilities Available
AD7804 Quad 10-Bit Serial Loading
AD7805 Quad 10-Bit Parallel Loading
AD7808 Octal 10-Bit Serial Loading
AD7809 Octal 10-Bit Parallel Loading
+3.3 V to +5 V Operation
Power-Down Mode
Power-On Reset
Standby Mode (All DACs/Individual DACs)
Low Power All CMOS Construction
10-Bit Resolution
Double Buffered DAC Registers
Dual External Reference Capability
APPLICATIONS
Optical Disk Drives
Instrumentation and Communication Systems
Process Control and Voltage Setpoint Control
Trim Potentiometer Replacement
Automatic Calibration
AD7804/AD7805/AD7808/AD7809
OUTPUT CHARACTERISTICS
DIGITAL INPUTS
REFERENCE OUTPUT
NOTES
(AVDD and DVDD = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V;
Reference = Internal Reference; CL = 100 pF; RL = 2 kV to GND. Sub DAC at Midscale. All specifications TMIN to TMAX unless otherwise noted.)AD7804/AD7805–SPECIFICATIONS
NOTESTemperature range is –40°C to +85°C.
(AVDD and DVDD = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V;
Reference = Internal Reference; CL = 100 pF; RL = 2 kV to GND. Sub DAC at Midscale. All specifications TMIN to TMAX unless otherwise noted.)AD7808/AD7809–SPECIFICATIONS
AD7804/AD7805/AD7808/AD7809
AD7804/AD7805/AD7808/AD7809
(VDD = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V; Reference =
Internal Reference. All specifications TMIN to TMAX unless otherwise noted.)
NOTESSample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (VIL + VIH)/2.
Specifications subject to change without notice.
CLKIN(I)
FSIN(I)
SDIN(I)
CLR
LDAC1
t6A
1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.
LDAC2
Figure 1.Timing Diagram for AD7804 and AD7808
AD7804/AD7808 TIMING CHARACTERISTICS1
AD7805/AD7809 TIMING CHARACTERISTICS1(VDD = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V; Reference
= Internal Reference. All specifications TMIN to TMAX unless otherwise noted.)
NOTESample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (VIL + VIH)/2.
Specifications subject to change without notice.
MODE
DATA
LDAC2
CLR
LDAC1
1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.
A0, A1, A2
Figure 2.Timing Diagram for AD7805/AD7809 Parallel Write
AD7804/AD7805/AD7808/AD7809
PDIP (N-24) Package, Power Dissipation . . . . . . . . . 670 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC (R-28) Package, Power Dissipation . . . . . . . . . 875 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PDIP (N-28) Package, Power Dissipation . . . . . . . . . 875 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SSOP (RS-28) Package, Power Dissipation . . . . . . . . 875 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
TQFP (ST-44B) Package, Power Dissipation . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded.Transient currents of up to 100 mA will not cause SCR latch-up.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V + 0.3 V
Digital Input Voltage to DGND . . . . .–0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . . .–0.3 V to AVDD + 0.3 V
COMP to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to + AVDD
REF IN to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies3 . . . . . . . . –10 mA
Operating Temperature Range
AD7804/AD7805 Commercial Plastic
(B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD7808/AD7809 Commercial Plastic
(B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SOIC (R-16) Package, Power Dissipation . . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PDIP (N-16) Package, Power Dissipation . . . . . . . . . 670 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC (R-24) Package, Power Dissipation . . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD7804/AD7808 PIN FUNCTION DESCRIPTION
14, 15
AD7804 PIN CONFIGURATION
AGND
VOUTB
VOUTA
REFOUT
FSIN
LDAC
SDIN
DGND
AVDD
VOUTC
VOUTD
COMP
REFIN
CLR
CLKIN
DVDD
AD7808 PIN CONFIGURATION
NC = NO CONNECT
DGND
SDIN
LDAC
FSIN
VOUTE
AGND
VOUTB
VOUTA
REFOUT
VOUTF
AGND
DVDD
CLKIN
CLR
VOUTH
AVDD
VOUTC
VOUTD
COMP
VOUTG
AVDD
REFIN
AD7804/AD7805/AD7808/AD7809
AD7805/AD7809 PIN FUNCTION DESCRIPTIONS
AD7805 PIN CONFIGURATION
DB2
DB3
LDAC
DB4
DB5
DB6
AGND
VOUTB
VOUTA
REFOUT
DB7
DB8
DB9
CLR
DB1
DB0
AVDD
VOUTC
VOUTD
COMP
MODE
REFIN
AD7809 PIN CONFIGURATION
TERMINOLOGY
Relative Accuracy
For the DACs, relative accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func-
tion. Figures 32 and 33 show the linearity at 3 V and 5 V
respectively.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of –1 LSB maxi-
mum ensures monotonicity.
Bias Offset Error
If the DACs are ideal, the output voltage of any DAC with
midscale code loaded will be equal to VBIAS where VBIAS is se-
lected by MX1 and MX0 in the control register. The DAC bias
offset error is the difference between the actual output voltage
and VBIAS, expressed in mV.
Gain Error
The difference between the actual and ideal analog output
range, expressed as a percent of full-scale range. It is the devia-
tion in slope of the DAC transfer characteristic from ideal.
Zero-Scale Error
The zero-scale error is the actual output minus the ideal output
from any DAC when zero code is loaded to the DAC. If offset
binary coding is used, the code loaded is 000Hex, and if twos
complement coding is used, a code of 200HEX is loaded to the
DAC to calculate the zero-scale error. Zero-scale error is ex-
pressed in mV.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the digital inputs change state with the
DAC selected and the LDAC used to update the DAC. It is
normally specified as the area of the glitch in nV-s and is mea-
sured when the digital input code is changed by 1 LSB at the
major carry transition. Regardless of whether offset binary or twos
complement coding is used, the major carry transition occurs at
the analog output voltage change of VBIAS to VBIAS – 1 LSB
or vice versa.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital inputs of the same
DAC but is measured when the DAC is not updated. It is speci-
fied in nV secs and is measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one converter due to a digital code change to another DAC.
It is specified in nV-s.
Analog Crosstalk
Analog crosstalk is a change in output of any DAC in response
to a change in the output of one or more of the other DACs. It
is measured in LSBs.
Power Supply Rejection Ratio (PSRR)
This specification indicates how the output of the DAC is af-
fected by changes in the power supply voltage. Power-supply
rejection ratio is quoted in terms of % change in output per %
change in VDD for full-scale output of the DAC. VDD is varied10%.
AD7804/AD7808 INTERFACE SECTION
The AD7804 and AD7808 are serial input devices. Three lines
control the serial interface, FSIN, CLKIN and SDIN. The timing
diagram is shown in Figure 1.
Two mode bits (MD1 and MD0) which are DB13 and DB14 of
the serial word written to the AD7804/AD7808 are used to deter-
mine whether writing is to the DAC data registers or the control
registers of the device. These parts contain a system control
register for controlling the operation of all DACs in the package
as well as a channel control register for controlling the operation of
each individual DAC. Table I shows how to access these registers.
Table I.Register Selection Table for the AD7804/AD7808
When the FSIN input goes low, data appearing on the SDIN
line is clocked into the input register on each falling edge of
CLKIN. Data to be transferred to the AD7804/AD7808 is
loaded MSB first. Figure 4 shows the loading sequence for the
sequence for the channel control register write, and Figures 6
and 7 show the sequence for loading data to the Main and Sub
DAC data registers. Figure 3 shows the internal registers associ-
ated with the AD7804/AD7808 serial interface DACs. Only one
DAC structure is shown for clarity.INTERNAL VREF
VDD/2
REFIN
VOUT
FSIN
TO ALL
CHANNELS
SINGLE
CHANNEL
Figure 3.AD7804/AD7808 Internal Registers
AD7804/AD7805/AD7808/AD7809
DB15 (MSB)DB0 (LSB)
X = Don’t Care
*Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804.
Figure 5.AD7804/AD7808 Channel Control Register Loading Sequence
DB15 (MSB)DB0 (LSB)
X = Don’t Care
*Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804.
Figure 6.AD7804/AD7808 Main DAC Data Register Loading Sequence (MAIN/SUB = 0)
DB15 (MSB)DB0 (LSB)
X = Don’t Care
*Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804.
Figure 7.AD7804/AD7808 Sub DAC Data Register Loading Sequence (MAIN/SUB = 1)
MSB LSB
X = Don’t Care
Figure 4.AD7804/AD7808 System Control Register Loading Sequence
AD7804/AD7808 SYSTEM CONTROL REGISTER (MD1 = 0,
MD0 = 0)
The bits in this register allow control over all DACs in the
package. The control bits include power down (PD), DAC input
coding select (BIN/COMP), system standby (SSTBY) and a
system clear (SCLR). The function of these bits is as follows:
Power Down (PD)
This bit in the control register is used to shut down the complete
device. With a 0 in this position, the reference and all DACs are
put into low power mode. Writing a 1 to this bit puts the part in
the normal operating mode. When in power-down mode, the
contents of all registers are retained and are valid when the
device is put back into normal operation.
Coding (BIN/COMP)
This bit in the system control register allows the user to select
one of two input coding schemes. The available schemes are
Twos complement coding and offset binary coding. All DACs
will be configured with the same input coding scheme. Writing
a zero to the control register selects twos complement coding,
while writing a 1 to this bit in the control register selects offset
binary coding.
With twos complement coding selected the output voltage from
the Main DAC is of the form :
where
With Offset Binary coding selected the output voltage from the
When the system control register is selected by writing zeros to
the mode bits, MD1 and MD0 the address bits are ignored as
the system control register controls all DACs in the package.
When MD1 = 0 and MD0 = 1, writing is to the channel control
register. Only the DAC selected by the address bits will be af-
fected by writing to this register. Each individual DAC has a
channel control register.
The DACs data registers are addressed by writing a one to
MD1 (DB13); the condition of MD0 (DB14) does not matter
when writing to the data registers. DB15 determines whether
writing is to the Main DAC data register or to the Sub DAC
data register. The Main DAC is 10 bits wide and the Sub DAC
is 8 bits wide. Thus when writing to the Sub DAC DB1 and
DB0 become don’t cares. The Sub DAC is used to offset the
complete transfer function of the Main DAC around its VBIAS
point. The Sub DAC has 1/8 LSB resolution and will enable the
transfer function of the Main DAC to be offset by – VBIAS/32.
When the LDAC line goes low, all DAC registers in the device
are simultaneously loaded with the contents of their respective
DAC data registers, and the outputs change accordingly.
Bringing the CLR line low resets the DAC data and DAC regis-
ters. This hardware clear affects both the Main and Sub DACs.
This operation sets the analog output of the Main DAC to VBIAS/
16 when offset binary coding is selected and the output is set to
VBIAS when twos complement coding is used. VBIAS is the output
of the internal multiplexer as shown in Figure 3. The output of
the Sub DAC is used to shift the transfer function of the Main
DAC around the VBIAS point and the contribution from the Sub
DAC is zero following an external hardware clear. Software
VBIAS can be the internal bandgap reference, the internal VDD/2
reference or the external REFIN as determined by MX1 and
MX0 in the channel control register. A second external refer-
ence can be used if required by overdriving the VDD/2 reference
which appears at the COMP pin.
System Standby (SSTBY)
This bit allows all the DACs in the package to be put into low
power mode simultaneously but the reference is not affected.
Writing a one to the SSTBY bit in the system control register
puts all DACs into standby mode. On writing a one to this bit
all linear circuitry is switched off and the DAC outputs are
connected through a high impedance to ground. The DACs come
out of standby mode when a 0 is written to the SSTBY bit.
System Clear Function (SCLR)
This function allows the user to clear the contents of all data
and DAC registers in software. Writing a one to the SCLR bit
in the control register clears the DAC’s outputs. A zero in this
bit position puts the DAC in normal operating mode. The out-
put of the Main DACs are cleared to one of two voltages de-
pending on the input coding used. If twos complement coding
is selected, then issuing a software clear will reset the output of
the Main DAC to midscale (VBIAS). If offset binary coding is
selected, the Main DAC output will be reset to VBIAS /16 follow-
ing the execution of a software clear. This system clear function
does not affect the Sub DAC; the Sub DAC data register retains
its value during a system software clear (SCLR).
AD7804/AD7808 CHANNEL CONTROL REGISTER (MD1 = 0,
MD0 = 1)
This register allows the user to have control over individual
DACs in the package. The control bits in this register include
the address bits for the selected DAC, standby (STBY), indi-
vidual DAC clear (CLR) and multiplexer output selection
(MX1 and MX0). The function of these bits follows.
DAC Selection (A2, A1, A0)
Bits A2, A1 and A0 in the input registers are used to address a
specific DAC. Table IIa shows the selection table for the DACs
of the AD7804. Table IIb shows the selection table for the
DACs of the AD7808.
Table IIa.DAC Selection Table for the AD7804
Table IIb.DAC Selection Table for the AD7808
Standby (STBY)
This bit allows the selected DAC in the package to be put into
low power mode. Writing a zero to the STBY bit in the channel
control register puts the selected DAC into standby mode. On
writing a zero to this bit all linear circuitry is switched off and
the DAC output is connected through a high impedance to
ground. The DAC is returned to normal operation by writing a
one to the STBY bit.
Software Clear Function (CLR)
This function allows the user to clear the contents of the se-
lected DAC’s data in software. Writing a one to the CLR bit in
the control register clears the DAC’s output. A zero in the CLR
bit position puts the DAC in normal operating mode. This
software CLR operation clears only the Main DAC, the con-
tents of the Sub DAC is unaffected by a CLR operation. The
output of the Main DAC can be cleared to one of two places
depending on the input coding used. An LDAC pulse is re-
quired to activate the channel clear function and must be ap-
plied after the bit in the channel control register is set or reset. If
twos complement coding is selected, then issuing a software
clear will reset the output of the Main DAC to midscale (VBIAS).
If offset binary coding is selected, the Main DAC output will be
reset to VBIAS/16 following the execution of a software clear.
Multiplexer Selection (MX1, MX0)
These two bits are used to select the reference input for the
selected DAC. Table III shows the options available.
Table III.Multiplexer Output Selection
AD7804/AD7808 SUB DAC DATA REGISTER
Figure 7 shows the loading sequence for writing to the data
registers of the DACs. DB15 determines whether writing is to
the Main or Sub DAC’s data register. A one in this position
selects the addressed Sub DAC’s data register. The Sub DAC is
8 bits wide and thus DB1 and DB0 of the 16-bit input word are
don’t cares when writing to the Sub DAC. This Sub DAC al-
lows the complete transfer function of each individual DAC to
be offset around the VBIAS point. This is achieved by either
adding or subtracting to the output of the Main DAC. This Sub
DAC has a span of –VBIAS/32 with 1/8-bit resolution. The
coding scheme for the Sub DAC is the same as that for the
Main DAC. With offset binary coding the transfer function for
the Sub DAC is
where NB is the digital code written to the Sub DAC and varies
from 0 to 255.
With twos complement coding the transfer function for the Sub
DAC is
AD7804/AD7805/AD7808/AD7809
determined by MX1 and MX0 in the channel control register as
shown in Table III. The internal VDD/2 reference is provided at
the COMP pin. This internal reference can be overdriven with
an external reference thus providing the facility for two external
references.
AD7804/AD7808 POWER-UP CONDITIONS
When power is applied to the device, the device will come up in
standby mode where all the linear circuitry excluding the refer-
ence are switched off. Figure 8 shows the relevant default val-
ues for the system control register. Since a write to the system
control register is required to remove the standby condition the
only bits for which default conditions are applicable are PD and
SSTBY. Figure 9 details the relevant default conditions for the
Channel Control Register.
Figure 8.Default Conditions for System Control Register
on Power-Up
Figure 9.Default Conditions for Channel Control Register
on Power-Up
After power has been applied to the device the following proce-
dure should be followed to communicate and set up the device.
First, a write to the system control register is required to clear
the SSTBY bit and change the input coding scheme if required.
For example, to remove standby and set up offset binary input
coding 0060Hex should be written to the input register, if twos
complement coding is required 0020Hex should be written to
the input register. MD1 and MD0 are decoded in the input
register and this allows the data to be written to the system
control register.
Step two requires writing to the channel control register, which
allows individual control over each DAC in the package and
allows the VBIAS for the DAC to be selected as well as individual
DAC standby and clear functions. For example, if channel A is
to be configured for normal operation with internal reference
selected then 4110Hex should be written to the input register.
In the input register, the MD1 and MD0 bits are decoded in
association with the address bits to give access to the required
channel control register. The third and final step is to write data
to the selected DAC. To write half scale to channel A Main
DAC, 2200Hex should be written to the input register, the
MSB in the sixteen bit stream selects the Main DAC and the
next three bits address the DAC and the final 10 bits contain
the data. To write half scale to channel A Sub DAC, then A200
should be written to the input register. The flowchart in Figure
10 shows in graphic form the steps required in communicating
with the AD7804/AD7808.
Figure 10.Flowchart for Controlling the DAC Following
Power-Up
AD7805/AD7809 INTERFACE SECTION
The AD7805 and AD7809 are parallel data input devices and
contain both control registers and data registers. The system
control register has global control over all DACs in the package
while the channel control register allows control over individual
DACs in the package. Two data registers are also available, one
for the 10-bit Main DAC and the second for the 8-bit Sub
DAC. In the parallel mode, CS and WR, in association with the
address pins, control the loading of data. Data is transferred
from the data register to the DAC register under the control of
the LDAC signal. Only data contained in the DAC register deter-
mines the analog output of any DAC. The timing diagram for
10-bit parallel loading is shown in Figure 2. The MODE pin on
the device determines whether writing is to the data registers or
to the control registers. When MODE is at a logic one, writing
is to the data registers. In the next write to the data registers a
bit in the channel control register determines whether the Main
DAC or the Sub DAC is addressed. This means that to address
either the Main or the Sub DAC the Main/Sub bit in the control
register has to be set appropriately before the data register write.
A logic zero on the mode pin enables writing to the control
register. Bit MD0 determines whether writing is to the system
control register or to the addressed channel control register.
Bringing the CLR line low resets the DAC registers to one of
DB9 DB0
X = Don’t Care
Figure 14.AD7805/AD7809 Main DAC Data Register (Top)
and Sub DAC Data Register (Bottom) Configuration
(MODE = 1, 10/8 = 0)
Figure 15 shows the bit allocations when 8-bit parallel operation
is selected in the system control register. DB9 to DB2 are re-
tained as data bits. DB1 acts as a high byte or low byte enable.
When DB1 is low, the eight MSBs of the data word are loaded
to the input register. When DB1 is high, the low byte consisting
of the two LSBs are loaded to the input register. DB0 is used to
select either the Main or Sub DAC when in the byte mode.
DB9 DB2 DB1 DB0
X = Don’t Care
Figure 15.AD7805/AD7809 Main DAC Data Register Con-
figuration (MODE = 1, 10/8 = 1, MAIN/SUB = 0)
Figure 16 shows the bit allocations for writing to the Sub DAC.
DB9 DB2DB1 DB0
X = Don’t Care
Figure 16.AD7805/AD7809 Sub DAC Data Register Con-
figuration (MODE = 1, MAIN/SUB = 1)
Each DAC has a separate channel control register. The follow-
ing is a brief discussion on the bits in each of the control registers.
DAC Selection (A2, A1, A0)
The external address pins in conjunction with CS, WR and
MODE are used to address the various DAC data and control
registers. Table IVa shows how these DAC registers can be
addressed on the AD7805. Table IVb shows how these registers
are addressed on the AD7809. Refer to Figures 12 to 16 for infor-
mation on the registers.
Table IVa.AD7805 DAC Data/Control Register
Selection Table
of the Main DAC to the bottom of the transfer function, VBIAS/16.
With twos complement coding the output of the DAC is cleared
to midscale which is VBIAS. A hardware clear always clears the
output of the Sub DAC to midscale thus the output of the Sub
DAC makes zero contribution to the output of the channel.D2D1D0MODEADDR
VBIASINTERNAL VREF
VDD/2
REFIN
VOUT
TO ALL
CHANNELS
SINGLE
CHANNELWR
LDAC
Figure 11.AD7805/AD7809 Internal Registers
AD7805/AD7809 CONTROL REGISTERS
Access to the control registers of the AD7805/AD7809 is
achieved by taking the mode pin to a logic low. The control
register of these DACs are configured as in Figures 12 and 13.
There are two control registers associated with the part. System
control register which looks after the input coding, data format,
power down, system clear and system standby. The channel
control register contains bits that affect the operation of the
selected DAC. The external address bits are used to select the
DACs. These registers are eight bits wide and the last two bits
are control bits. The mode pin must be low to have access to the
control registers.
DB9 DB2 DB1 DB0
X = Don’t Care
Figure 12.AD7805/AD7809 System Control Register Con-
figuration, (MODE = 0)
DB9 DB2 DB1 DB0
X = Don’t Care
Figure 13. AD7805/AD7809 Channel Control Register Con-
figuration (MODE = 0)
The external mode pin must be taken high to allow data to be
written to the DAC data registers. Figure 14 shows the bit allo-
cations when 10-bit parallel operation is selected in the system
control register.
AD7804/AD7805/AD7808/AD7809
Table IVb.AD7809 DAC Data/Control Register
Selection Table
AD7805/AD7809 SYSTEM OR CHANNEL CONTROL
REGISTER SELECTION
MD0This enables writing to the system control register.
The contents of this are shown in Figure 12. Mode
must be low to access this control register.This enables writing to the channel control register.
The contents of this are shown in Figure 13. Mode
must also be low to access this control register.
AD7805/AD7809 SYSTEM CONTROL REGISTER
The bits in this register allow control over all DACs in the pack-
age. The control bits include data format (10/8), power down
(PD), DAC input coding select (BIN/COMP), system standby
(SSTBY) and a system clear (SCLR). The function of these bits
is as follows:
Data Format10/810-bit parallel loading structure.Byte loading structure. (8+2 loading).
Input Coding
BIN/COMPTwos complement coding.Offset Binary Coding.
Power DownPDComplete power-down of device.Normal operation (default on power-up).
System Standby
SSTBYNormal operation.
System Clear
SCLRNormal operation.All DACs in the package are cleared to a known state
depending on the coding scheme selected. The SCLR bit
clears the Main DACs only; the Sub DACs are unaf-
fected by the system clear function. The main DAC is
cleared to different levels depending on the coding
scheme. With offset binary coding the Main DAC output
is cleared to the bottom of the transfer function VBIAS/16.
With twos complement coding the Main DAC output is
cleared to midscale VBIAS. The channel output will be the
sum of the Main DAC and Sub DAC contributions.
AD7805/AD7809 CHANNEL CONTROL REGISTER
This register allows the user to have control over individual
DACs in the package. The control bits in this register include
multiplexer output selection (MX1 and MX0), Main or Sub
DAC selection (MAIN/SUB), standby (STBY) and individual
DAC clear (CLR). The function of these bits is as follows.
Multiplexer Selection (MX1, MX0)
Table V shows the VBIAS selection using MX1 and MX0 bits in
the channel control register.
Table V.VBIAS Selection Table
Main DAC or Sub DAC SelectionMAIN/SUBWriting a 0 to this bit means that the data in the next
data register write is transferred to the selected Main
DAC.Writing a 1 to this bit means that the data in the next
data register write is transferred to the selected Sub DAC.
This applies to the 10-bit parallel load feature. In byte
load mode, (Figure 15) DB0 selects the Main or Sub
DAC data registers.
StandbySTBYPlaces the selected DAC and its associated linear cir-
cuitry in Standby Mode.Normal operation (default on power-up).
Clear
CLRNormal operation.Clears the output of the selected Main DAC to one
of two conditions depending on the input coding se-
lected. With offset binary coding the Main DAC out-
put is cleared to the bottom of the transfer function,
VBIAS/16 and with twos complement coding the Main

Partno	Mfg	Dc	Qty	Available	Descript
AD7804BN	AD	N/a	224	avai	+3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7804BR	ADI	N/a	21	avai	+3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7805BN		N/a	18	avai	+3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7805BR	AD	N/a	3181	avai	+3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7805BRS	ANALOG	N/a	30	avai	+3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7805CR	ADI	N/a	600	avai	+3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7808BR	AD	N/a	15	avai	+3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7809BST	ADI	N/a	90	avai	+3.3 V to +5 V Quad/Octal 10-Bit DACs