AD7801BR-AD7801BRU Fast Delivery |IC PHOENIX CO.,LIMITED

AD7801BRU ,+2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DACapplications.buffer allows the DAC output to swing rail to rail. The AD7801has a parallel microproc ..
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AD7804BN ,+3.3 V to +5 V Quad/Octal 10-Bit DACsFeatures Channels Controlled Main DAC Sub DACDATA DACCHANNEL BHardware Clear All ÏÏREGISTER REGISTE ..
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AD7804BRZ , 3.3 V to 5 V Quad/Octal 10-Bit DACs
AD7805BN ,+3.3 V to +5 V Quad/Octal 10-Bit DACsSPECIFICATIONS (AV and DV = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V;DD DDReference = Internal R ..
ADM1818-5ART-REEL7 , Microprocessor Reset Circuits
ADM1818-5ART-REEL7 , Microprocessor Reset Circuits
ADM1818-5ART-REEL7 , Microprocessor Reset Circuits
ADM1818-R22ART-RL7 , Microprocessor Reset Circuits
ADM1818-R22ART-RL7 , Microprocessor Reset Circuits
ADM202EAN ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversGENERAL DESCRIPTIONNOTE*INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUTThe ADM202E and ADM1181 ..

AD7801BR-AD7801BRU
+2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC
REV.0
+2.7 V to +5.5 V, Parallel Input,
Voltage Output 8-Bit DAC
FUNCTIONAL BLOCK DIAGRAM
VOUT
AGNDCLRLDACREFINVDDDGND
FEATURES
Single 8-Bit DAC
20-Pin SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer Rail-to-Rail Operation
Low Power Operation 1.75 mA max @ 3.3 V
Power-Down to 1 mA max @ 258C
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD7801 is a single, 8-bit, voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision output
buffer allows the DAC output to swing rail to rail. The AD7801
has a parallel microprocessor and DSP compatible interface with
high speed registers and double buffered interface logic. Data is
loaded to the input register on the rising edge of CS or WR.
Reference selection for the AD7801 can be either an internal
reference derived from the VDD or an external reference applied
at the REFIN pin. The output of the DAC can be cleared by
using the asynchronous CLR input.
The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consump-
tion is less than 5 mW at 3.3 V, reducing to less than 3 μW in
power-down mode.
The AD7801 is available in a 20-lead SOIC and a 20-lead
TSSOP package.
PRODUCT HIGHLIGHTSLow Power, Single Supply operation. This part operates
from a single +2.7 V to +5.5 V supply and consumes typically
5 mW at 3 V, making it ideal for battery powered applications.The on-chip output buffer amplifier allows the output of the
DAC to swing rail to rail with a settling time of typically 1.2 μs.Internal or external reference capability.High speed parallel interface.Power-down capability. When powered down the DAC
consumes less than 1 μA at 25°C.Packaged in 20-lead SOIC and TSSOP packages.
AD7801–SPECIFICATIONS
(VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 kV to VDD and GND.
All specifications TMIN to TMAX unless otherwise noted.)
STATIC PERFORMANCE
LOGIC INPUTS
POWER REQUIREMENTS
NOTESTemperature ranges are as follows: B Version: –40°C to +105°CRelative Accuracy is calculated using a reduced code range of 15 to 245.Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.Guaranteed by characterization at product release, not production tested.
Specifications subject to change without notice.
D7-D0
LDAC
TIMING CHARACTERISTICS1, 2
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of
(VIL + VIH)/2. tr and tf should not exceed 1 μs on any digital input.See Figure 1.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7801 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Reference Input Voltage to AGND . . . .–0.3 V to VDD + 0.3V
Digital Input Voltage to DGND . . . . . .–0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . .700 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .143°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . .870 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .74°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
*R = Small Outline; RU = Thin Shrink Small Outline.
(VDD = +2.7 V to +5.5 V; GND = 0 V; Internal VDD/2 Reference. All specifications TMIN to TMAX
unless otherwise noted.)
AD7801
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
NC = NO CONNECT
(MSB) DB7
AGND
VOUT
DGND
DB6
DB5
DB4
CLR
VDD
REFINDB3
DB2
DB1
(LSB) DB0DGND
LDAC
SINK CURRENT – mA
OUT
– mV
480
Figure 2.Output Sink Current Capa-
bility with VDD = 3 V and VDD = 5 V
REFERENCE VOLTAGE – Volts
ERROR – LSBs
0.3
Figure 5.Relative Accuracy vs.
External Reference
FREQUENCY – Hz
ATTENUATION – dB1010k1001k
–35
Figure 8.Large Scale Signal
Frequency Response
Figure 3.Output Source Current
Capability with VDD = 5 V
TEMPERATURE – C
– mA
0.5255075125
Figure 6.Typical Supply Current
vs. Temperature‹‹‹
CH1 5V, CH2 1V, CH3 20mV
TIME BASE = 200 ns/Div
Figure 9.Full-Scale Settling Time
SOURCE CURRENT – mA
OUT
– Volts
Figure 4.Output Source Current
Capability with VDD = 3 V
VDD – Volts
– mA
2.0
Figure 7.Typical Supply Current
vs. Supply Voltage
CH1 = 2V/div, CH2 = 5V/Div,
TIME BASE = 2 ms/Div
Figure 10.Exiting Power-Down (Full
Power-Down)
AD7801
Figure 11.Power-On—Reset
INPUT CODE (15 to 245)
INL ERROR – LSB256326496128160192224
0.5
Figure 14.Integral Linearity Plot
–Typical Performance Characteristics
ZERO CODE ERROR – LSB
Figure 12.Zero Code Error vs.
Temperature
INL ERROR – LSB
TEMPERATURE – C
Figure 15.Typical INL vs. Temperature‹‹
CH1 5.00V, CH2 50.0mV, M 250ns
Figure 13.Small-Scale Settling Time
TEMPERATURE – C
DNL ERROR – LSB
Figure 16.Typical DNL vs. Temperature
TEMPERATURE – C
INT REFERENCE ERROR – 0.8
1.0
Figure 17.Typical Internal Reference
Error vs. Temperature
TEMPERATURE – C
POWER DOWN CURRENT – nA255075100
Figure 18.Power-Down Current vs.
Temperature
TERMINOLOGY
Integral Nonlinearity
For the DAC, Relative Accuracy or End-Point nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A graphical representation of the transfer curve is
shown in Figure 14.
Differential Nonlinearity
Differential Nonlinearity is the difference between the mea-
sured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity.
Zero-Code Error
Zero-Code Error is the measured output voltage from VOUT of
the DAC when zero code (all zeros) is loaded to the DAC
latch. It is due to a combination of the offset errors in the DAC
and output amplifier. Zero-code error is expressed in LSBs.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale value. It includes full-
scale errors but not offset errors.
Digital-to-Analog Glitch Impulse
Digital-to-Analog Glitch Impulse is the impulse injected into
the analog output when the digital inputs change state with
the DAC selected and the LDAC used to update the DAC. It
is normally specified as the area of the glitch in nV-secs and
measured when the digital input code is changed by 1 LSB at
the major carry transition.
Digital Feedthrough
Digital Feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital inputs of the same
DAC, but is measured when the DAC is not updated. It is
specified in nV-secs and measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa.
Power Supply Rejection Ratio (PSRR)
This specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power supply rejection
ratio is quoted in terms of % change in output per % change in
VDD for full-scale output of the DAC. VDD is varied ±10%.
GENERAL DESCRIPTION
D/A Section
The AD7801 is an 8-bit voltage output digital-to-analog con-
verter. The architecture consists of a reference amplifier and a
current source DAC followed by a current-to-voltage converter
capable of generating rail-to-rail voltages on the output of the
DAC. Figure 19 shows a block diagram of the basic DAC
architecture.
VOUTREFIN
Figure 19.DAC Architecture
The DAC output is internally buffered and has rail-to-rail
output characteristics. The output amplifier is capable of driving
a load of 100 pF and 10 kΩ to both VDD and ground. The
reference selection for the DAC can be either internally gener-
ated from VDD or externally applied through the REFIN pin. A
comparator on the REFIN pin detects whether the required
reference is the internally generated reference or the externally
applied voltage to the REFIN pin. If REFIN is connected to
VDD, the reference selected is the internally generated VDD/2
reference. When an externally applied voltage is more than one
volt below VDD, the comparator selection switches to the externally
applied voltage on the REFIN pin. The range on the external
reference input is from 1.0 V to VDD/2 V. The output voltage
from the DAC is given by:
where VREF is the voltage applied to the external REFIN pin or
VDD/2 when the internal reference is selected. N is the decimal
equivalent of the code loaded to the DAC register and ranges
from 0 to 255.INT REF
EXT REF
Figure 20.Reference Selection Circuitry
AD7801
Reference
The AD7801 has the ability to use either an external reference
applied through the REFIN pin or an internal reference generated
from VDD. Figure 20 shows the reference input arrangement
where either the internal VDD/2 or the externally applied reference
can be selected.
The internal reference is selected by tying the REFIN pin to
VDD. If an external reference is to be used, this can be directly
applied to the REFIN pin and if this is 1 V below VDD, the
internal circuitry will select this externally applied reference as
the reference source for the DAC.
Digital Interface
The AD7801 contains a fast parallel interface allowing this
DAC to interface to industry standard microprocessors,
microcontrollers and DSP machines. There are two modes in
which this parallel interface can be configured to update the
DAC output. The synchronous update mode allows synchro-
nous updating of the DAC output; the automatic update mode
allows the DAC to be updated individually following a write
cycle. Figure 21 shows the internal logic associated with the
digital interface. The PON STRB signal is internally generated
from the power-on reset circuitry and is low during the power-
on reset phase of the power up procedure.
PON STRB
CLR
LDAC
Figure 21.Logic Interface
The AD7801 has a double buffered interface, which allows for
synchronous updating of the DAC output. Figure 22 shows a
block diagram of the register arrangement within the AD7801.
LDAC
CLR
DB7-DB0
Figure 22.Register Arrangement
Automatic Update Mode
In this mode of operation the LDAC signal is permanently tied
low. The state of the LDAC is sampled on the rising edge of
WR. LDAC being low allows the DAC register to be automati-
cally updated on the rising edge of WR. The output update
occurs on the rising edge of WR. Figure 23 shows the timing
associated with the automatic update mode of operation and
also the status of the various registers during this frame.
D7-D0
LDAC = 0
I/P REG (MLE)
DAC REG (SLE)
VOUT
Figure 23.Timing and Register Arrangement for Auto-
matic Update Mode
Synchronous Update Mode
In this mode of operation the LDAC signal is used to update the
DAC output to synchronize with other updates in the system.
The state of the LDAC is sampled on the rising edge of WR. If
LDAC is high, the automatic update mode is disabled and the
DAC latch is updated at any time after the write by taking
LDAC low. The output update occurs on the falling edge of
LDAC. LDAC must be taken back high again before the next
data transfer takes place. Figure 24 shows the timing associated
with the synchronous update mode of operation and also the
status of the various registers during this frame.
D7-D0
LDAC
I/P REG (MLE)
DAC REG (SLE)
VOUT
Figure 24.Timing and Register Arrangement for Synchro-
nous Update Mode

Partno	Mfg	Dc	Qty	Available	Descript
AD7801BR	AD	N/a	253	avai	+2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC
AD7801BRU	AD	N/a	525	avai	+2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC