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AD7793BRU
3-Channel, Low Noise, Low Power, 16-Bit Sigma-Delta A/D Converters with On-Chip In-Amp and Reference
3-Channel, Low Noise, Low Power, 16/24-Bit∑-Δ ADC with On-Chip In-Amp and Reference
Rev. 0
FEATURES
Up to 22.5 bits effective resoluion
RMS noise: 40 nV @ 4.17 Hz 85 nV @ 16.7 Hz
Current: 400 µA typ
Power-down: 1 µA max
Low noise programmable gain instrumentation-amp
Band gap reference with 4 ppm/°C drift typ
Update rate: 4.17 Hz to 500 Hz
3 differential inputs
Internal clock oscillator
Simultaneous 50 Hz/60 Hz rejection
Programmable current sources
On-chip bias voltage generator
Burnout currents
Power supply: 2.7 V to 5.25 V
–40°C to +105°C temperature range
Independent interface power supply
16-lead TSSOP package
INTERFACE
3-wire serial
SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
Schmitt trigger on SCLK
APPLICATIONS
Thermocouple measurements
RTD measurements
Thermistor measurements
Gas analysis
Industrial process control
Instrumentation
Portable instrumentation
Blood analysis
Smart transmitters
Liquid/gas chromotography
6-digit DVM
FUNCTIONAL BLOCK DIAGRAM DOUT/RDY
DIN
SCLK
DVDD
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
CLK
GNDAVDDREFIN(–)/AIN3(–)
IOUT1
IOUT2
REFIN(+)/AIN3(+)
Figure 1.
GENERAL DESCRIPTION The AD7792/AD7793 is a low power, low noise, complete
analog front end for high precision measurement applications.
The AD7792/AD7793 contains a low noise 16/24-bit ∑-∆ ADC
with three differential analog inputs. The on-chip, low noise
instrumentation amplifier means that signals of small ampli-
tude can be interfaced directly to the ADC. With a gain
setting of 64, the rms noise is 40 nV when the update rate
equals 4.17 Hz.
The device contains a precision low noise, low drift internal
band gap reference and can also accept an external differential
reference. Other on-chip features include programmable excita-
tion current sources, burnout currents, and a bias voltage gener-
ator, the bias voltage generator being used to set the common-
mode voltage of a channel to AVDD/2.
The device can be operated with the internal clock or, alterna-
tively, an external clock can be used. The output data rate from
the part is software-programmable and can be varied from
4.17 Hz to 500 Hz.
The part operates with a power supply from 2.7 V to 5.25 V. It
consumes a current of 400 µA typical and is housed in a 16-lead
TSSOP package.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Characteristics.....................................................................6
Absolute Maximum Ratings............................................................8
ESD Caution..................................................................................8
Pin Configuration and Function Descriptions.............................9
Output Noise and Resolution Specifications..............................11
External Reference......................................................................11
Internal Reference......................................................................12
Typical Performance Characteristics...........................................13
On-Chip Registers..........................................................................14
Communications Register.........................................................14
Status Register.............................................................................15
Mode Register.............................................................................15
Configuration Register..............................................................17
Data Register...............................................................................18
ID Register...................................................................................18
IO Register...................................................................................18
Offset Register.............................................................................19
Full-Scale Register......................................................................19
ADC Circuit Information..............................................................20
Overview.....................................................................................20
Digital Interface..........................................................................21
Circuit Description.........................................................................24
Analog Input Channel...............................................................24
Instrumentation Amplifier........................................................24
Bipolar/Unipolar Configuration..............................................24
Data Output Coding..................................................................24
Burnout Currents.......................................................................25
Excitation Currents....................................................................25
Bias Voltage Generator..............................................................25
Reference.....................................................................................25
Reset.............................................................................................25
AVDD Monitor.............................................................................26
Calibration...................................................................................26
Grounding and Layout..............................................................26
Applications.....................................................................................28
Temperature Measurement using a Thermocouple...............28
Temperature Measurement using an RTD..............................29
Outline Dimensions.......................................................................30
Ordering Guide..........................................................................30
REVISION HISTORY
10/04—Revision 0: Initial Version SPECIFICATIONS AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
1 Temperature range –40°C to +105°C. Specification is not production tested but is supported by characterization data at initial product release.
3 Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected. Recalibration at any temperature removes these errors.
5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, Gain = 1, TA = 25°C). FS[3:0] are the four bits used in the mode register to select the output word rate.
7 Digital inputs equal to DVDD or GND with excitation currents and bias voltage generator disabled.
TIMING CHARACTERISTICS AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, input logic 0 = 0 V, input logic 1 = DVDD, unless otherwise noted.
Table 2. 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2 See Figure 3 and Figure 4. These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is falling edge of SCLK. These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
ISINK (1.6mA WITH DVDD = 5V,
100µA WITH DVDD = 3V)
ISOURCE (200µA WITH DVDD = 5V,
100µA WITH DVDD = 3V)
1.6VOUTPUTPIN
50pF
Figure 2. Load Circuit for Timing Characterization
CS (I)
DOUT/RDY (O)
SCLK (I)
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
04855-004
I = INPUT, O = OUTPUT
CS (I)
DIN (I)Figure 4. Write Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 3. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONSSCLKDIN
CLKDOUT/RDYDVDD
IOUT1AVDD
AIN1(+)GNDIOUT2
AIN2(+)REFIN(–)/AIN3(–)REFIN(+)/AIN3(+)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
OUTPUT NOISE AND RESOLUTION SPECIFICATIONS
EXTERNAL REFERENCE Table 5 shows the AD7792/AD7793’s output rms noise for some
of the update rates and gain settings. The numbers given are for
the bipolar input range with an external 2.5 V reference. These
numbers are typical and are generated with a differential input
voltage of 0 V. Table 6 and Table 7 show the effective resolution
while the output peak-to-peak (p-p) resolution is shown in
brackets for the AD7793 and AD7792, respectively. It is
important to note that the effective resolution is calculated
using the rms noise, while the p-p resolution is based on the
p-p noise. The p-p resolution represents the resolution for
which there is no code flicker. These numbers are typical and
are rounded to the nearest LSB.
Table 5. Output RMS Noise (µV) vs. Gain and Output Update Rate for the AD7792 and AD7793 Using an External 2.5 V Reference
Table 6. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7793 Using an External 2.5 V Reference
Table 7. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7792 Using an External 2.5 V Reference
INTERNAL REFERENCE Table 8 shows the AD7792/AD7793’s output rms noise for some
of the update rates and gain settings. The numbers given are for
the bipolar input range with the internal 1.17 V reference. These
numbers are typical and are generated with a differential input
voltage of 0 V. Table 9 and Table 10 show the effective resolu-
tion, while the output peak-to-peak (p-p) resolution is given in
brackets for the AD7793 and AD7792, respectively. It is
important to note that the effective resolution is calculated
using the rms noise, while the p-p resolution is calculated based
on p-p noise. The p-p resolution represents the resolution for
which there is no code flicker. These numbers are typical and
are rounded to the nearest LSB.
Table 8. Output RMS Noise (µV) vs. Gain and Output Update Rate for the AD7792 and AD7793 Using the Internal Reference
Table 9. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7793 Using the Internal Reference
Table 10. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7792 Using the Internal Reference TYPICAL PERFORMANCE CHARACTERISTICS
83887501000800600400200READING NUMBER
CODE
RE
Figure 6. Typical Noise Plot (Internal Reference, Gain = 64,
Update Rate = 16.7 Hz) for AD7793
83884828388750838872083886808388640838860083885608388520OCCURANCE
Figure 7. Noise Distribution Histogram for AD7793
(Internal Reference, Gain = 64, Update Rate = 16.7 Hz)
–2.0–1.2–0.8–0.400.40.81.21.62.0MATCHING (%)
(%)
–1.75–1.05–0.70–0.3500.350.701.051.401.75MATCHING (%)
(%)
Figure 9. Excitation Current Matching (1 mA) at Ambient Temperature
02004006008001000LOAD CAPACITANCE (nF)
POW
TIM
Figure 10. Bias Voltage Generator Power-Up Time vs. Load Capacitance
0.500.51.01.52.02.53.03.54.04.55.0REFERENCE VOLTAGE (V)
S N
ISE (
ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER
RS2, RS1, RS0 = 0, 0, 0 The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the
communications register. The data written to the communications register determines whether the next operation is a read or write
operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to
the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the
default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the
communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN
high returns the ADC to this default state by resetting the entire part. Table 11 outlines the bit designations for the communications
register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of
the data stream. The number in brackets indicates the power-on/reset default status of that bit.
Table 11. Communications Register Bit Designations
Table 12. Register Selection
STATUS REGISTER
RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7792)/0x88 (AD7793) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bits RS2, RS1 and RS0 with 0. Table 13 outlines the bit designations for the status register.
SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status of that bit.
Table 13. Status Register Bit Designations
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the
operating mode, update rate, and clock source. Table 14 outlines the bit designations for the mode register. MR0 through MR15 indicate
the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets
indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit.
Table 14. Mode Register Bit Designations
Table 15. Operating Modes
Table 16. Update Rates Available
