AD7790BRMZ ,16-Bit, Single-Channel, Ultra Low Power, Sigma Delta A/D Converterapplications varied from 9.5 Hz to 120 Hz, with the rms noise equal to Portable instrumentation 1.1 ..
AD7791BRM ,24-Bit, Single-Channel, Ultra Low Power, Sigma Delta A/D Converterapplications varied from 9.5 Hz to 120 Hz, with the rms noise equal to Portable instrumentation 1.1 ..
AD7793BRU ,3-Channel, Low Noise, Low Power, 24-Bit Sigma-Delta ADC with On-Chip In-Amp and Referencefeatures include programmable excita-Thermocouple measurements tion current sources, burnout curren ..
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ADM1817-5ART-REEL7 ,Microprocessor Supervisory in SOT-23 with Active High Push-Pull OutputSPECIFICATIONS(V = Full Operating Range, T = –40C to +105C, unless otherwise noted.)CC AParameter ..
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ADM1818-20AKS-RL7 ,Microprocessor Supervisory in SOT-23 with Manual Push Button OptionSPECIFICATIONS(V = Full Operating Range, T = –40C to +105C, unless otherwise noted.)CC AParameter ..
AD7790BRMZ
16-Bit, Single-Channel, Ultra Low Power, Sigma Delta A/D Converter
Low Power, 16-Bit
Buffered Sigma-Delta ADC
Rev. 0
FEATURES
Power
Supply: 2.5 V to 5.25 V operation
Normal: 75 µA maximum
Power-down: 1 µA maximum
RMS noise: 1.1 µV at 9.5 Hz update rate
16-bit p-p resolution
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
Programmable gain amplifier
Rail-to-rail input buffer
VDD monitor channel
Temperature range: –40°C to +105°C
10-lead MSOP
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
FUNCTIONAL BLOCK DIAGRAM GNDREFIN
VDD
Figure 1.
GENERAL DESCRIPTION The AD7790 is a low power, complete analog front end for
low frequency measurement applications. It contains a low
noise 16-bit ∑-∆ ADC with one differential input that can be
buffered or unbuffered along with a digital PGA, which allows
gains of 1, 2, 4, and 8.
The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate from the part is software programmable and can be
varied from 9.5 Hz to 120 Hz, with the rms noise equal to
1.1 µV at the lower update rate. The internal clock frequency
can be divided by a factor of 2, 4, or 8, which leads to a reduc-
tion in the current consumption. The update rate, cutoff
frequency, and settling time will scale with the clock frequency.
The part operates with a power supply from 2.5 V to 5.25 V.
When operating from a 3 V supply, the power dissipation for
the part is 225 µW maximum. It is housed in a 10-lead MSOP.
TABLE OF CONTENTS AD7790—Specifications..................................................................3
Timing Characteristics.....................................................................5
Absolute Maximum Ratings............................................................7
Pin Configuration and Function Descriptions.............................8
Typical Performance Characteristics.............................................9
On-Chip Registers..........................................................................10
Communications Register
(RS1, RS0 = 0, 0).........................................................................10
Status Register
(RS1, RS0 = 0, 0; Power-on/Reset = 0x88)...............................11
Mode Register
(RS1, RS0 = 0, 1; Power-on/Reset = 0x02)...............................11
Filter Register
(RS1, RS0 = 1, 0; Power-on/Reset = 0x04)...............................12
Data Register
(RS1, RS0 = 1, 1; Power-on/Reset = 0x0000)..........................12
ADC Circuit Information..............................................................13
Overview.....................................................................................13
Noise Performance.....................................................................13
Reduced Current Modes...........................................................13
Digital Interface..........................................................................14
Single Conversion Mode.......................................................15
Continuous Conversion Mode.............................................15
Continuous Read Mode........................................................16
Circuit Description.........................................................................17
Analog Input Channel...............................................................17
Programmable Gain Amplifier.................................................17
Bipolar Configuration................................................................17
Data Output Coding..................................................................17
Reference Input...........................................................................17
VDD Monitor................................................................................18
Grounding and Layout..............................................................18
Outline Dimensions.......................................................................19
REVISION HISTORY Revision 0: Initial Version
AD7790—SPECIFICATIONS1
Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; CDIV1 = CDIV0 = 0; GND = 0 V;
all specifications TMIN to TMAX, unless otherwise noted.) 1 Temperature Range –40°C to +105°C. Specification is not production tested, but is supported by characterization data at initial product release.
3 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (VDD = 4 V). FS[2:0] are the three bits used in the filter register to select the output word rate.
SPECIFICATIONS (continued)1 5 Digital inputs equal to VDD or GND. The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 15).
TIMING CHARACTERISTICS1, 2
Table 2. (VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,
Input Logic 1 = VDD, unless otherwise noted.) Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 3 and Figure 4. These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is falling edge of SCLK. These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances. RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
ISINK (1.6mA WITH VDD = 5V,100µA WITH VDD = 3V)
ISOURCE (200µA WITH VDD = 5V,
100µA WITH VDD = 3V)
1.6VTO OUTPUT
PIN
50pF
Figure 2. Load Circuit for Timing Characterization
CS (I)
DOUT/RDY (O)
SCLK (I)
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
I = INPUT, O = OUTPUT
CS (I)
SCLK (I)
DIN (I)
Figure 4. Write Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 3. (TA= 25°C, unless otherwise noted.) Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD7790
TOP VIEW
(Not to Scale)
SCLK
AIN(+)
AIN(–)
REF(+)
DIN
DOUT/RDY
VDD
GND
REF(–)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS FREQUENCY (Hz)
Figure 6. Frequency Response for a 16.6 Hz Update Rate
S N
ISE (
VREF (V)Figure 7. RMS Noise vs. Reference Voltage
ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-
munications register. The data written to the communications register determines whether the next operation is a read or write operation,
and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of
the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-
ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to
this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi-
cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
Table 5. Communications Register Bit Designations
Table 6. Register Selection
Table 7. Channel Selection
