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AD7788ARM-AD7789BRM
Low Power, 16-/24-Bit Sigma-Delta ADC
Low Power, 16-/24-Bit
Sigma-Delta ADC
Rev. 0
FEATURES
AD7788: 16-bit resolution
AD7789: 24-bit resolution
Power
Supply: 2.5 V to 5.25 V operation
Normal: 75 µA maximum
Power-down: 1 µA maximum
RMS noise: 1.5 µV
AD7788: 16-bit p-p resolution
AD7789: 19-bit p-p resolution (21.5 bits effective)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
VDD monitor channel
10-lead MSOP
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
FUNCTIONAL BLOCK DIAGRAM *AD7788: 16-BIT ADC AD7789: 24-BIT ADC
AIN(+)
AIN(–)
GND
REFIN(+)REFIN(–)
DOUT/RDY
DIN
SCLK
Figure 1.
GENERAL DESCRIPTION The AD7788/AD7789 are low power, low noise, analog front
ends for low frequency measurement applications. The AD7789
contains a low noise 24-bit ∑-∆ ADC with one differential input.
The AD7788 is a 16-bit version of the AD7789.
The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate is 16.6 Hz, which gives simultaneous 50 Hz/60 Hz
rejection.
The part operates with a single power supply from 2.5 V to
5.25 V. When operating from a 3 V supply, the power dissipation
for the part is 225 µW maximum. The AD7788/AD7789 is
housed in a 10-lead MSOP.
TABLE OF CONTENTS AD7789—Specifications..................................................................3
AD7788—Specifications..................................................................4
AD7788/AD7789 Specifications.....................................................5
Timing Characteristics.....................................................................6
Absolute Maximum Ratings............................................................8
Pin Configuration and Function Descriptions.............................9
Typical Performance Characteristics...........................................10
On-Chip Registers..........................................................................11
Communications Register
(RS1, RS0 = 0, 0).........................................................................11
Status Register
(RS1, RS0 = 0, 0; Power-on/Reset = 0x88 [AD7788]
and 0x8C [AD7789])..................................................................12
Mode Register
(RS1, RS0 = 0, 1; Power-on/Reset = 0x02)...............................12
Data Register
(RS1, RS0 = 1, 1; Power-on/Reset = 0x0000 [AD7788]
and 0x000000 [AD7789])..........................................................13
ADC Circuit Information..............................................................14
Overview.....................................................................................14
Noise Performance.....................................................................14
Digital Interface..........................................................................14
Single Conversion Mode.......................................................15
Continuous Conversion Mode.............................................15
Continuous Read Mode........................................................16
Circuit Description.........................................................................17
Analog Input Channel...............................................................17
Bipolar/Unipolar Configuration..............................................17
Data Output Coding..................................................................17
Reference Input...........................................................................17
VDD Monitor................................................................................18
Grounding and Layout..............................................................18
Outline Dimensions.......................................................................19
REVISION HISTORY Revision 0: Initial Version
AD7789—SPECIFICATIONS1
Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V;
all specifications TMIN to TMAX, unless otherwise noted.) Temperature Range –40°C to +105°C.
2 Specification is not production tested, but is supported by characterization data at initial product release. Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).
AD7788—SPECIFICATIONS1
Table 2. (VDD = 2.5 V to 5.25 V (B Grade); VDD = 2.7 V to 5.25 V (A Grade); REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V;
all specifications TMIN to TMAX, unless otherwise noted.) Temperature Range: B Grade, –40°C to +105°C; A Grade, –40°C to +85°C.
AD7788/AD7789 SPECIFICATIONS
Table 3. 1 Specification is not production tested but is supported by characterization data at initial product release. Digital inputs equal to VDD or GND.
TIMING CHARACTERISTICS1, 2
Table 4. (VDD = 2.5 V to 5.25 V (AD7788B and AD7789), VDD = 2.7 V to 5.25 V (AD7788A); GND = 0 V, REFIN(+) = 2.5 V,
REFIN(–) = GND, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.) 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4.
3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. SCLK active edge is falling edge of SCLK.
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
ISINK (1.6mA WITH VDD = 5V,100µA WITH VDD = 3V)
ISOURCE (200µA WITH VDD = 5V,
100µA WITH VDD = 3V)
1.6VTO OUTPUT
PIN
50pF
Figure 2. Load Circuit for Timing Characterization
CS (I)
DOUT/RDY (O)
SCLK (I)
I = INPUT, O = OUTPUTFigure 3. Read Cycle Timing Diagram
I = INPUT, O = OUTPUT
CS (I)
SCLK (I)
DIN (I)
Figure 4. Write Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 5. (TA= 25°C, unless otherwise noted.) Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD7788/AD7789
TOP VIEW
(Not to Scale)
SCLK
AIN(+)
AIN(–)
REF(+)
DIN
DOUT/RDY
VDD
GND
REF(–)
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS FREQUENCY (Hz)
Figure 6. Frequency Response with 16.6 Hz Update Rate
OCCURE
NCE
8388625CODE
Figure 7. AD7789 Noise Histogram
CODE
READ NO.
Figure 8. AD7789 Noise Plot
S N
ISE (
VREF (V)Figure 9. AD7788/AD7789 Noise vs. VREF
