AD7776AR-AD7777AR-AD7778AS Fast Delivery |IC PHOENIX CO.,LIMITED

AD7776AR ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications T to T unless otherwise noted.)REFIN MIN MAX1Parameter A Versions Units Conditions/C ..
AD7777AR ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications T to T unless otherwise noted.)CC MIN MAXParameter Label Limit at T to T Units Test ..
AD7778AS ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications in bold print are 100% production tested. All other times are guaranteed by design, ..
AD7788ARM ,Low Power, 16-/24-Bit Sigma-Delta ADCCharacteristics .......... 10 Continuous Read Mode . 16 On-Chip Registers........ 11 Circuit Descri ..
AD7788ARMZ , Low Power, 16-/24-Bit, Sigma-Delta ADCs
AD7788ARMZ , Low Power, 16-/24-Bit, Sigma-Delta ADCs
ADM1815-10ARTZ-RL7 ,Microprocessor Supervisory in SOT-23 with Active Low Push-Pull Output ChoicesFEATURES FUNCTIONAL BLOCK DIAGRAMSReliable Low Cost Voltage Monitor with Reset OutputSuitable for M ..
ADM1815-20ART-RL7 ,Microprocessor Reset CircuitsSPECIFICATIONS(T = –408C to +858C unless otherwise noted)AParameter Min Typ Max Units Test Conditio ..
ADM1815-20ART-RL7 ,Microprocessor Reset CircuitsSPECIFICATIONS(T = –408C to +858C unless otherwise noted)AParameter Min Typ Max Units Test Conditio ..
ADM1815-20ARTZ-RL7 ,Microprocessor Supervisory in SOT-23 with Active Low Push-Pull Output ChoicesSpecifications subject to change without notice.–2– REV. CADM1810–ADM1813/ADM1815–ADM1818ABSOLUTE M ..
ADM1815-5AKS-RL7 ,Microprocessor Supervisory in SOT-23 with Active Low Push-Pull Output ChoicesMicroprocessor Reset CircuitsADM1810–ADM1813/ADM1815–ADM1818
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AD7776AR-AD7777AR-AD7778AS
LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs
REV.0LC2MOS, High Speed
1-, 4- & 8-Channel 10-Bit ADCs
FUNCTIONAL BLOCK DIAGRAMSRDWRBUSY/INTAGND
DB0–DB9
DGND
CLKIN
REFOUT
REFIN
CREFIN
RTN
AIN1
VCC
AGND
DB0–DB9
DGND
CLKIN
REFOUT
REFIN
CREFIN
AIN1
AIN2
AIN3
AIN4
VCC
RTN
AGND
DB0–DB9
DGND
CLKINRDWRBUSY/INT
REFOUT
REFIN
CREFIN
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
VCC
RTN
FEATURES
AD7776: Single Channel
AD7777: 4-Channel
AD7778: 8-Channel
Fast 10-Bit ADC: 2.5 ms Worst Case
+5 V Only
Half-Scale Conversion Option
Fast Interface Port
Power-Down Mode
APPLICATIONS
HDD Servos
Instrumentation
GENERAL DESCRIPTION
The AD7776, AD7777 and AD7778 are a family of high speed,
multichannel, 10-bit ADCs primarily intended for use in R/W
head positioning servos found in high density hard disk drives.
They have unique input signal conditioning features that make
them ideal for use in such single supply applications.
By setting a bit in a control register within both the four-channel
version, AD7777, and the eight-channel version, AD7778, the
input channels can either be independently sampled or any two
channels of choice can be simultaneously sampled. For all ver-
sions the specified input signal range is of the form VBIAS ±
VSWING. However, if the RTN pin is biased at, say, 2 V the
analog input signal range becomes 0 V to +2 V for all input
channels. This is covered in more detail under the section
Changing the Analog Input Voltage Range. The voltage VBIAS
is the offset of the ADC’s midpoint code from ground and is
supplied either by an onboard reference available to the user
(REFOUT) or by an external voltage reference applied to
REFIN. The full-scale range (FSR) of the ADC is equal to
2 VSWING where VSWING is nominally equal to REFIN/2. Addi-
tionally, when placed in the half-scale conversion mode, the
value of REFIN is converted. This allows the channel offset(s)
to be measured.
Control register loading and ADC register reading, channel se-
lect and conversion start are under the control of the μP. The
twos complemented coded ADCs are easily interfaced to a stan-
dard 16-bit MPU bus via their 10-bit data port and standard
microprocessor control lines.
The AD7776/AD7777/AD7778 are fabricated in linear compat-
ible CMOS (LC2MOS), an advanced, mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. The AD7776 is available in a 24-pin SOIC package; the
AD7777 is available in both 28-pin DIP and 28-pin SOIC pack-
ages; the AD7778 is available in a 44-pin PQFP package.
*. Patent No. 4,990,916.
AD7776/AD7777/AD7778–SPECIFICATIONS (VCC = +5 V 6 5%; AGND = DGND = O V;
CLKIN = 8 MHz; RTN = O V; CREFIN = 10 nF; all specifications TMIN to TMAX unless otherwise noted.)
REFERENCE OUTPUT
DYNAMIC PERFORMANCE
NOTESTemperature range as follows: A = –40°C to +85°C.
TIMING SPECIFICATIONS1, 2(VCC = +5 V 6 5%; AGND = DGND = 0 V; all specifications TMIN to TMAX unless otherwise noted.)
FIRST
CONVERSION
FINISHED
(CR6 = 0)
SECOND
CONVERSION
FINISHED (CR6 = 1)
AD7777/AD7778 ONLY
BUSY
(CR8 = 0)
INT
(CR8 = 1)
WR, RD
Figure 3.BUSY/INT Timing
Figure 4.Load Circuit for Bus Timing Characteristics
DB0–DB9
Figure 1.Read Cycle Timing
DB0–DB9
Figure 2.Write Cycle Timing
NOTESSee Figures 1 to 3.Timing specifications in bold print are 100% production tested. All other times are guaranteed by design, not production tested. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t4 is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.t5 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured time is then extrapolated back
to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t5 quoted above is the true bus relinquish time of the device and, as
such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.
AD7776/AD7777/AD7778
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VCC to AGND or DGND . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
AGND, RTN to DGND . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
CS, RD, WR, CLKIN, DB0–DB9,
BUSY/INT to DGND . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
Analog Input Voltage to AGND . . . . . . .–0.3 V, VCC + 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
Operating Temperature Range
All Versions . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .+150°C
DIP Package, Power Dissipation . . . . . . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . .+260°C
SOIC Packages, Power Dissipation . . . . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
PQFP Package, Power Dissipation . . . . . . . . . . . . . .500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATIONS
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7776/AD7777/AD7778 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
24-Pin SOIC7
DB2
DB3
DGND
DB4
DB5
DB6
DB7
DB1
DB0CREFIN
AGND
RTN
REFIN
AIN
AGND
REFOUT
VCC
DB8
(MSB) DB9
CLKIN
BUSY/INTRD
28-Pin DIP & SOIC
DB2
DB3
DGND
DB4
DB5
DB6
DB7
DB1
DB0
DB8
(MSB) DB9
BUSY/INT
CREFIN
AGND
RTN
REFIN
AGND
REFOUT
VCC
CLKIN
AIN4
AIN3
AIN2
AIN1
ORDERING GUIDE
44-Pin PQFPNCNCNCNCNC
DB2
DB3
DGND
DB4
DB5
DB6
DB7
DB1DB0C
REFIN
RTNAGND
REFIN
AIN8
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AGND
REFOUT
VCC
DB8
(MSB) DB9
CLKIN
BUSY/INT
NC = NO CONNECT
PIN FUNCTION DESCRIPTION
AGND
DGND
DB0–DB9
REFIN
CREFIN
CIRCUIT DESCRIPTION
ADC Transfer Function
For all versions, an input signal of the form VBIAS ± VSWING is
expected. This VBIAS signal level operates as a pseudo ground to
which all input signals must be referred. The VBIAS level is de-
termined by the voltage applied to the REFIN pin. This can be
driven by an external voltage source or, alternatively, the on-
board 2 V reference, available at REFOUT, can be used. The
magnitude of the input signal swing is equal to VBIAS/2 (or
REFIN/2) and is set internally. With a REFIN of 2 V, the analog
input signal level varies from 1 V up to 3 V i.e., 2 ± 1 V. Fig-
ure 5 shows the transfer function of the ADC and its relation-
ship to VBIAS and VSWING. The half-scale twos complement code
of the ADC, 000 Hex (00 0000 0000 Binary), occurs at an input
voltage equal to VBIAS. The input full-scale range of the ADC is
equal to 2 VSWING, so that the Plus Full-Scale transition (1FE to
1FF) occurs at a voltage equal to VBIAS + VSWING – 1.5 LSBs
and the minus full-scale code transition (200 to 201) occurs at
a voltage VBIAS – VSWING + 0.5 LSBs.
ADC
OUTPUT
CODE
(HEX)
1FF
1FE
VBIAS–VSWING
VBIAS
VBIAS+VSWINGANALOG INPUT, VIN
Figure 5.ADC Transfer Function
AD7776/AD7777/AD7778
CR6: Determines whether operation is on a single channel or
simultaneous sampling on two channels. Location CR6 is a
“don’t care” for the AD7776.
CR6FunctionSingle channel operation. Channel select
address is contained in locations CR0–CR2.Two channels simultaneously sampled
and sequentially converted. Channel
select addresses contained in locations
CR0–CR2 and CR3–CR5.
CR7: Determines whether the device is in the normal operating
mode or in the half-scale test mode.
CR7FunctionNormal Operating ModeHalf-Scale Test Mode
In the half-scale test mode REFIN is internally connected as an
analog input(s). In this mode locations CR0–CR2 and CR3–
CR5 are all “don’t cares” since it is REFIN which will be con-
verted. For the AD7777 and AD7778, the contents of location
CR6 still determine whether a single or a double conversion is
carried out on the REFIN level.
CR8: Determines whether the device is in the normal operating
mode or in the powerdown mode.
CR8FunctionNormal Operating ModePowerdown Mode
In the powerdown mode all linear circuitry is turned off and the
REFOUT output is weakly (5 kΩ) pulled to AGND. The input
impedance of the analog inputs and of the REFIN input re-
mains the same in either normal mode or powerdown mode. See
under Circuit Description—Powerdown Mode.
CR9: Determines whether BUSY/INT output flag goes low and
remains low during conversion(s) or else goes low and remains
low after the conversion(s) is (are) complete.
CR9BUSY/INT FunctionalityOutput goes low and remains low during
conversion(s).Output goes low and remains low after conversion(s)
is (are) complete.
ADC Conversion Start Timing
Figure 6 shows the operating waveforms for the start of a con-
version cycle. On the rising edge of WR, the conversion cycle
starts with the acquisition and tracking of the selected ADC
channel, AIN1–8. The analog input voltage is held 40 ns (typi-
cally) after the first rising edge of CLKIN following four com-
plete CLKIN cycles. If tD in Figure 6 is greater than 12 ns, the
falling edge of CLKIN as shown will be seen as the first falling
clock edge. If tD is less than 12 ns, the first falling clock edge to
be recognized will not occur until one cycle later.
Following the “hold” on the analog input(s), two complete
CLKIN cycles are allowed for settling purposes before the MSB
decision is made. The actual decision point occurs approximately
40 ns after the rising edge of CLKIN as shown in Figure 6. A
further two CLKIN cycles are allowed for the second MSB
CONTROL REGISTER
The control register is 10-bits wide and can only be written to.
On power-on, all locations in the control register are automati-
cally loaded with 0s. For the single channel AD7776, locations
CR0 to CR6 of the control register are “don’t cares.” For the
quad channel AD7777, locations CR2 and CR5 are “don’t
cares.” Individual bit functions are described below.
CR0–CR2: Channel Address Locations. Determines which channel
will be selected and converted for single channel operation. For si-
multaneous sampling operation CR0–CR2 holds the address of one
of the two channels to be sampled.
AD7776
CR2CR1CR0FunctionXXSelect AIN1
*X = Don’t Care
AD7777
CR2CR1CR0Function00Select AIN101Select AIN210Select AIN311Select AIN4
*X = Don’t Care
AD7778
CR2CR1CR0Function00Select AIN101Select AIN210Select AIN311Select AIN400Select AIN501Select AIN610Select AIN711Select AIN8
CR3–CR5: Channel Address Locations. Only applicable for simul-
taneous sampling with the AD7777 or AD7778 when CR3–CR5
holds the address of the second channel to be sampled.
AD7777
CR5CR4CR3Function00Select AIN101Select AIN210Select AIN311Select AIN4
*X = Don’t Care
AD7778
CR5CR4CR3Function00Select AIN101Select AIN210Select AIN311Select AIN400Select AIN501Select AIN610Select AIN7

Partno	Mfg	Dc	Qty	Available	Descript
AD7776AR	AD	N/a	855	avai	LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs
AD7777AR	AD	N/a	107	avai	LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs
AD7778AS		N/a	6	avai	LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs