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AD7776AR ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications T to T unless otherwise noted.)REFIN MIN MAX1Parameter A Versions Units Conditions/C ..
AD7777AR ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications T to T unless otherwise noted.)CC MIN MAXParameter Label Limit at T to T Units Test ..
AD7778AS ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications in bold print are 100% production tested. All other times are guaranteed by design, ..
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AD7776
High Speed 1-, 4- & 8-Channel 10-Bit CMOS ADCs
REV. A
LC2MOS, High Speed
1-, 4-, and 8-Channel 10-Bit ADCs
FUNCTIONAL BLOCK DIAGRAMSRDWR BUSY/INTAGND
DB0–DB9
DGND
CLKIN
REFOUT
REFIN
CREFIN
RTN
AIN1
VCC
AGND
DB0–DB9
DGND
CLKIN
REFOUT
REFIN
CREFIN
AIN1
AIN2
AIN3
AIN4
VCC
RTN
AGND
DB0–DB9
DGND
CLKINRDWR BUSY/INT
REFOUT
REFIN
CREFIN
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
VCC
RTN
FEATURES
AD7776: 1-Channel
AD7777: 4-Channel
AD7778: 8-Channel
Fast 10-Bit ADC: 2.5 �s Worst Case
+5 V Only
Half-Scale Conversion Option
Fast Interface Port
Power-Down Mode
APPLICATIONS
HDD Servos
Instrumentation
GENERAL DESCRIPTIONThe AD7776/AD7777/AD7778 are a family of high speed,
multichannel, 10-bit ADCs primarily intended for use in R/W
head positioning servos found in high density hard disk drives.
They have unique input signal conditioning features that make
them ideal for use in such single supply applications.
By setting a bit in a control register within both the four-channel
version, AD7777, and the eight-channel version, AD7778, the
input channels can either be independently sampled or any two
channels can be simultaneously sampled. For all versions, the
specified input signal range is of the form VBIAS ± VSWING.
However, if the RTN pin is biased at, for example, 2 V the
analog input signal range becomes 0 V to +2 V for all input
channels. This is covered in more detail under the section
Changing the Analog Input Voltage Range. The voltage VBIAS is
the offset of the ADC’s midpoint code from ground and is
supplied either by an onboard reference available to the user
(REFOUT) or by an external voltage reference applied to
REFIN. The full-scale range (FSR) of the ADC is equal to
2 VSWING where VSWING is nominally equal to REFIN/2. Addi-
tionally, when placed in the half-scale conversion mode, the
value of REFIN is converted. This allows the channel offset(s)
to be measured.
Control register loading and ADC register reading, channel select
and conversion start are under the control of the µP. The twos
complement coded ADCs are easily interfaced to a standard 16-bit
MPU bus via their 10-bit data port and standard microprocessor
control lines.
The AD7776/AD7777/AD7778 are fabricated in linear compat-
ible CMOS (LC2MOS), an advanced, mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. The AD7776 is available in a 24-lead SOIC package; the
AD7777 is available in both 28-lead DIP and 28-lead SOIC
packages; the AD7778 is available in a 44-lead PQFP package.
*. Patent No. 4,990,916.
AD7776/AD7777/AD7778–SPECIFICATIONS
CLKIN = 8 MHz; RTN = O V; CREFIN = 10 nF; all specifications TMIN to TMAX unless otherwise noted.)DC ACCURACY
REFERENCE INPUT
LOGIC INPUTS
NOTESTemperature range as follows: A = –40°C to +85°C.
(VCC = +5 V � 5%; AGND = DGND = O V;
AD7776/AD7777/AD7778
TIMING SPECIFICATIONS1, 2(VCC = +5 V � 5%; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.)
FIRST
CONVERSION
FINISHED
(CR6 = 0)
SECOND
CONVERSION
FINISHED (CR6 = 1)
AD7777/AD7778 ONLY
BUSY
(CR8 = 0)
INT
(CR8 = 1)
WR, RDFigure 3.BUSY/INT Timing
Figure 4.Load Circuit for Bus Timing Characteristics
DB0–DB9Figure 1.Read Cycle Timing
DB0–DB9Figure 2.Write Cycle Timing
NOTESSee Figures 1 to 3.All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.100% production tested. All other times are guaranteed by design, not production tested.t4 is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.t5 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured time is then extrapolated back
to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t5 quoted above is the true bus relinquish time of the device and, as
such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.
AD7776/AD7777/AD7778
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VCC to AGND or DGND . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
AGND, RTN to DGND . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
CS, RD, WR, CLKIN, DB0–DB9,
BUSY/INT to DGND . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
Analog Input Voltage to AGND . . . . . . .–0.3 V, VCC + 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . . .–0.3 V, VCC + 0.3 V
Operating Temperature Range
All Versions . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
DIP Package, Power Dissipation . . . . . . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+260°C
SOIC Packages, Power Dissipation . . . . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
ORDERING GUIDE*R = SOIC, N = PDIP, S = PQFP
PQFP Package, Power Dissipation . . . . . . . . . . . . . .500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
*Stresses above those listed under absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PIN CONFIGURATIONS
44-Lead PQFPNCNCNCNCNC
DB2
DB3
DGND
DB4
DB5
DB6
DB7
DB1DB0C
REFIN
RTNAGND
REFIN
AIN8
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AGND
REFOUT
VCC
DB8
(MSB) DB9
CLKIN
BUSY/INT
NC = NO CONNECT
24-Lead SOIC
28-Lead PDIP and SOIC
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7776/AD7777/AD7778 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONAGND
DGND
DB0–DB9
BUSY/INT
CIRCUIT DESCRIPTION
ADC Transfer FunctionFor all versions, an input signal of the form VBIAS ± VSWING is
expected. This VBIAS signal level operates as a pseudo ground to
which all input signals must be referred. The VBIAS level is
determined by the voltage applied to the REFIN pin. This can
be driven by an external voltage source or, alternatively, by the
onboard 2 V reference, available at REFOUT. The magnitude
of the input signal swing is equal to VBIAS/2 (or REFIN/2) and is
set internally. With a REFIN of 2 V, the analog input signal level
varies from 1 V to 3 V, i.e., 2 ± 1 V. Figure 5 shows the transfer
function of the ADC and its relationship to VBIAS and VSWING.
The half-scale two's complement code of the ADC, 000 Hex (00
0000 0000 Binary), occurs at an input voltage equal to VBIAS. The
input full-scale range of the ADC is equal to 2 VSWING, so that the
Plus Full-Scale transition (1FE to 1FF) occurs at a voltage equal to
VBIAS + VSWING – 1.5 LSBs, and the minus full-scale code transi-
tion (200 to 201) occurs at a voltage VBIAS – VSWING + 0.5 LSBs.
Figure 5.ADC Transfer Function
AD7776/AD7777/AD7778
AD7778
CR5CR4CR3Function0Select AIN11Select AIN20Select AIN31Select AIN40Select AIN51Select AIN60Select AIN71Select AIN8
CR6: Determines whether operation is on a single channel orsimultaneous sampling on two channels. Location CR6 is a
“don’t care” for the AD7776.
CR6FunctionSingle channel operation. Channel select
address is contained in locations CR0–CR2.Two channels simultaneously sampled
and sequentially converted. Channel
select addresses contained in locations
CR0–CR2 and CR3–CR5.
CR7: Determines whether the device is in the normal operatingmode or in the half-scale test mode.
CR7Function0Normal Operating Mode
1Half-Scale Test Mode
In the half-scale test mode, REFIN is internally connected as an
analog input(s). In this mode, locations CR0–CR2 and CR3–CR5
are all “don’t cares” since it is REFIN which is converted. For
the AD7777 and AD7778, the contents of location CR6 still
determine whether a single or a double conversion is carried out
on the REFIN level.
CR8: Determines whether the device is in the normal operatingmode or in the power-down mode.
CR8Function0Normal Operating ModePower-Down Mode
In the power-down mode all linear circuitry is turned off and the
REFOUT output is weakly (5 kΩ) pulled to AGND. The input
impedance of the analog inputs and of the REFIN input remains
the same in either normal mode or power-down mode. See
under Circuit Description—Power-Down Mode.
CR9: Determines whether BUSY/INT output flag goes low andremains low during conversion(s) or else goes low and remains
low after the conversion(s) is (are) complete.
CR9BUSY/INT FunctionalityOutput goes low and remains low during
conversion(s).Output goes low and remains low after conversion(s)
is (are) complete.
CONTROL REGISTERThe control register is 10-bit wide and can only be written to.
On power-on, all locations in the control register are automati-
cally loaded with 0s. For the single channel AD7776, locations
CR0 to CR6 of the control register are “don’t cares.” For the
quad channel AD7777, locations CR2 and CR5 are “don’t
cares.” Individual bit functions are described below.
CR0–CR2: Channel Address Locations. Determines which channelis selected and converted for single-channel operation. For simulta-
neous sampling operation, CR0–CR2 holds the address of one of
the two channels to be sampled.
AD7776
CR2CR1CR0FunctionXXSelect AIN1
*X = Don’t Care
AD7777
CR2CR1CR0Function00Select AIN11Select AIN20Select AIN31Select AIN4
*X = Don’t Care
AD7778
CR2CR1CR0Function0Select AIN11Select AIN20Select AIN31Select AIN40Select AIN51Select AIN60Select AIN71Select AIN8
CR3–CR5: Channel Address Locations. Only applicable for simul-taneous sampling with the AD7777 or AD7778 when CR3–CR5
holds the address of the second channel to be sampled.
AD7777
CR5CR4CR3Function00Select AIN11Select AIN20Select AIN31Select AIN4
*X = Don’t Care
