AD7775JR ,1W; V(cc): -0.3 to +7.0V; LC2MOS complete embedded servo front end for HDDFEATURES
10-Bit, 3 us ADC
Two DACs with Output Amplifiers
One 10-Bit, 4 us Settling DAC
One ..
AD7776 ,High Speed 1-, 4- & 8-Channel 10-Bit CMOS ADCsapplications.A 1INCONTROL REGISTERBy setting a bit in a control register within both the four-chann ..
AD7776AR ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications T to T unless otherwise noted.)REFIN MIN MAX1Parameter A Versions Units Conditions/C ..
AD7777AR ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications T to T unless otherwise noted.)CC MIN MAXParameter Label Limit at T to T Units Test ..
AD7778AS ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications in bold print are 100% production tested. All other times are guaranteed by design, ..
AD7788ARM ,Low Power, 16-/24-Bit Sigma-Delta ADCCharacteristics .......... 10 Continuous Read Mode . 16 On-Chip Registers........ 11 Circuit Descri ..
ADM1815-10ART-RL7 ,Microprocessor Reset CircuitsFEATURES FUNCTIONAL BLOCK DIAGRAMSReliable Low Cost Voltage Monitor with Reset OutputSupports Monit ..
ADM1815-10ARTZ-RL7 ,Microprocessor Supervisory in SOT-23 with Active Low Push-Pull Output ChoicesFEATURES FUNCTIONAL BLOCK DIAGRAMSReliable Low Cost Voltage Monitor with Reset OutputSuitable for M ..
ADM1815-20ART-RL7 ,Microprocessor Reset CircuitsSPECIFICATIONS(T = –408C to +858C unless otherwise noted)AParameter Min Typ Max Units Test Conditio ..
ADM1815-20ART-RL7 ,Microprocessor Reset CircuitsSPECIFICATIONS(T = –408C to +858C unless otherwise noted)AParameter Min Typ Max Units Test Conditio ..
ADM1815-20ARTZ-RL7 ,Microprocessor Supervisory in SOT-23 with Active Low Push-Pull Output ChoicesSpecifications subject to change without notice.–2– REV. CADM1810–ADM1813/ADM1815–ADM1818ABSOLUTE M ..
ADM1815-5AKS-RL7 ,Microprocessor Supervisory in SOT-23 with Active Low Push-Pull Output ChoicesMicroprocessor Reset CircuitsADM1810–ADM1813/ADM1815–ADM1818
AD7773JR-AD7775JR
1W; V(cc): -0.3 to +7.0V; LC2MOS complete embedded servo front end for HDD
ANALOG
DEVICES
tthas Complete Embedded
Servo Front Ends for HDD
M7773/h07775*
FEATURES
1o-Bit, 3 us ADC
Two DACs with Output Amplifiers
One 10-Bit, 4 us Settling DAC
One 8-Bit, 3 us Settling DAC
Fully Integrated Burst Demodulator
Power-Down Mode
+5 V Only
Fast Interface Port
28-Pin SOIC Package
APPLICATIONS
Embedded Servo For HDD
Combined Dedicated/Embedded Servo
GENERAL DESCRIPTION
The AD7773 and AD7775 provide all the functionality necessary
to implement the servo demodulator and head positioning tasks
in embedded servo systems, A power-down mode which turns
all the linear circuitry OF F enhances the use of the AD7773 and
AD7775 in portable systems.
The demodulator channel can capture high speed servo data
from a variety of embedded servo patterns. Up to four sequen-
tial servo burst signals can be synchronously demodulated, full-
wave rectified and integrated. At the end of a burst period the
integrated output voltage, representing the amplitude of a cap-
tured burst, is sampled and held on one of four internal track/
hold amplifiers prior to conversion. After conversion the digi-
tized burst signals from the ADC are fed to four lO-bit wide
data registers.
The AD7773 and AD7775 also contain two independent voltage-
output DACs: one with 10-bit resolution and one with 8-bit
resolution. The two DACs produce output signals of the form
VBIAS t szmo where VBIAS and szmo are internally gener-
ated on-chip. The VBIAS signal is available externally on the
REFOUT pin.
The devices are easily interfaced to popular DSP processors
and microcontrollers. The AD7773 has a 10-bit data port with
separate address pins. The AD7775 has a 10-bit multiplexed
address/data bus with an ALE input to latch the address.
The AD7773 and AD7775 are fabricated in linear compatible
CMOS (LCZCMOS), an advanced, mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. The devices are available in 28-pin SOIC packages and
32-pin TSOPs.
*. Patent No. 4,990,916.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAMS
C INT(‘) C m‘rM CLKIN Vcc
A A A f'\
v m (r) zcn & TRACK/ 1mm
RECTIFIER HOLD ADC
Vm H (x4)
ADCREG4
ADCREGS
DEMODULATOR ADCREG2
C cr- CONTROL LOGIC ADCREGI
STATUS
AD7773 REGISTER IO
m 10 DB9
CONTROL REGISTER F---- 1tFBIT
DAC A VourA
AO ADDRESS 4 8
Al & DECODE ,
DAC B Vour B
BUS INTERFACE
CONTROL LOGIC REF yams
REFOUT
I J, A A n
V \J U V V
cs m. 5 DGND AGND AGND
C m'rH C INT“) CLKIN Vcc
A f h A I h
N..' Y U
V," M zco & TRACK/ 1mm
RECTIF1ER H0CD - ADC
Vm (-) (x4)
ADCREGA
ADCREG3
DEMODULATOR ADCREG2
C RL C CONTROL LOGIC ADCREGI
STATUS
AD7775 REGISTER
10 DB9
V CONTROL REGISTER tr--- wan
ADDRESS le
ALE O DECODE
BUS INTERFACE
RESET CONTROL LOGIC REF
REFOUT
- - DGND AGND AGND
One Technology Way, P.O. Box 9106, Norwood, MA 02052-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/ 394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
h07malm75-SMlFliyfrl0lG
(IG, = +5 ll t 5%; AGND = DGND = il ll; CLKIN = 6.67 MHz;
em cr. 200 pF; Burst Frequency = 5 MHz; Cycles Integrated =
4. All spetrifitratitms u to Tm, unless othenvise stated.)
Parameter J Versionl Units Conditions/Comments
DEMODULATOR CHANNEL All AC Test Waveforms are Sinusoidal. Minimum
Signal Frequency Is 2 MHz.
ADC Resolution 10 Bits
Demodulator Channel Gain, GCH 352 LSBN p-p min Channel Gain is (384 t 32) LSBN p-p
416 LSBN p-p max
Intercept of Transfer Function on
ADC Code Axis, ADCINTCPT - 137/+ 35 LSB min/max See Terminology & Figure 19
Differential Input Resistance 4/6.5 k0 min/max Typically 5 kn; Measured at DC; See Terminology
Differential Input Capacitance" 1/4 pF min/max
Common-Mode Input Resistance 2/3.5 kft min/max Typically 2.5 k0; Measured at DC; See Terminology
Common-Mode Input Capacitance' 5/15 pF min/max
ZCD Differential Hysteresis, VH 40/120 mV p-p min/max Typically 55 mV; See Figure 20 under Design
Information
Frequency Response to Pulse Harmonics
2nd Harmonics :10 % typ See Terminology
3rd Harmonics t20 % typ
Common-Mode Rejection Ratio 46 dB min See Terminology
Power Supply Rejection Ratio2 40 dB min See Terminology
Channel Noise Level2 49 dB min See Terminology
Composite Noise Rejection2 38 dB min Referenced to Half-Scale; See Terminology
VIN) Differential Input Signal Range
for Guaranteed Positive Slope 0.24/2.26 V p-p min/max See Terminology
ADC Code for 0 mV p-p
Differential Input Voltage, ADCO +35 LSB max See Figure 19
ADC Code for 240 mV p-p
Differential Input Voltage, ADC240 ADC200 + 4 LSB min ADCzoo Is ADC Code for 200 mV p-p Differential
Input Voltage
ADC Code for 417 mV p-p
Differential Input Voltage, AD%, ADC0 + 10 LSB min
ADC Code for 2260 mV p-p
Differential Input Voltage, ADC2260 ADC2500 - 4 LSB min ADCzsoo Is ADC Code for 2500 mV p-p Differential
Input Voltage
ADC Code for 2500 mV p-p
Differential Input Voltage, ADC2500 1022 LSB max
Voltage Change Across CINT for
Full-Scale ADC Range REFOUT/2 V typ
Gm, Transconductance from VIN to
IOUT at CINT(+) 0.277/0.306 mS min/max
Relative Accuracy t4 LSB max 0.625 V to 1.875 V; See Terminology
t8 LSB max 0.417 V to 2.083 V
Differential Nonlinearity - 1.3/+2 LSB max Guaranteed Monotonic to 9 Bits; See Terminology
Channel Mismatch 10 LSB max Measured at Half-Scale; See Terminology
Crosstalk Between Bursts S LSB max See Terminology
ADC Conversion Time 14 TCLKIN us max Per Captured Burst; See Terminology
TCLKIN 0.15/0.5 115 min/max Period of Input Clock CLKIN
TCLKIN High2 60 ns min Minimum High Time for CLKIN
TCLKIN Low2 60 ns min Minimum Low Time for CLKIN
Output Coding Unipolar Binary
ANALOG OUTPUTS3
Output Voltage Range
Digital-to-Analog Glitch Impulse2
Digital Feedthrough2
DC Output Impedance"
Short-Circuit Current
Power Supply Rejection Ratio2
Input Coding
VBIAS - szmo
VBIAS + VSWING
nV sec typ
nV sec typ
mA max
dB min
Offset Binary/2s Complement
Applies to Both DACs
See Terminology
See Terminology
Typically 0.5 n
See Terminology
See Terminology
Programmable via Location CR6 of the Control
Register
REV. A
M7773/li07775
Parameter J Versionl Units Conditions/Comments
ANALOG OUTPUTS3 (Continued)
Resolution 10 Bits
Output Voltage Settling Time2 4 p.s max Settling Time to Within t 1/2 LSB of Final Value;
Typically 2.0 pm
Relative Accuracy tl LSB max
Differential Nonlinearity tl LSB max Guaranteed Monotonic
Bias Offset Error t20 LSB max
Plus or Minus Full-Scale Error :16 LSB max Referenced to REFOUT/2
Resolution 8 Bits
Output Voltage Settling Time2 3 515 max Settling Time to Within :1/2 LSB of Final Value;
Typically 2.0 us
Relative Accuracy tl LSB max
Differential Nonlinearity tl LSB max Guaranteed Monotonic
Bias Offset Error t6 LSB max
Plus or Minus Full-Scale Error t6 LSB max Referenced to REFOUT/2.
LOGIC INPUTS
(E W, It-lj, CTRL, CLKIN,
RESET & ALE (AD7775),
A0 & A1 (AD7773)
Input Low Voltage, VINL 0.8 V max
Input High Voltage, VINL 2.4 V min
Input Leakage Current 10 HA max
Input Capacitance' 10 pF max
LOGIC OUTPUTS
DBO-DB9 (AD7773)
ADO-DB9 (AD7775)
VOL, Output Low Voltage 0.4 V max ISINK = 1.6 mA
Vorr, Output High Voltage 4.0 V min ISOURCB = 200 wA
F loating State Leakage Current 10 " max
Floating State Capacitance 10 pF max
POWER REQUIREMENTS
Vcc Range 4.75/5.25 V min/V max For Specified Performance
ICC, Normal Mode4 30 mA max Control Register Locations CR8 = CR9 = Logic High
ICC, Power Down Modes 1.5 mA max Control Register Locations CR8 = Logic High,
CR9 = Logic Low; All Linear Circuitry OFF
Power-Up Time to Operational
Specifications" 500 us max From Power Down Mode
DAC REFERENCE INPUTS
VBIAS for both DACs REFOUT V Internally Connected. Available Externally on
REFOUT Pin
szmc for both DACs REFOUT/2 V Internally Connected
REFERENCE OUTPUT"'
REFOUT 2.1/2.2 V min/max
Reference Load Change t3 mV max For Reference Load Current Change of 0 to t500 wA
t5 mV max For Reference Load Current Change of 0 to t2 mA
Reference Load Should Not Change During Conversion
"Temperature range as follows: J Version: 0°C to +70°C.
'Guaranteed by design, not production tested.
3Output load of 10k1100 pF is referenced to REFOUT. - --.- -
'Input signal levels are as follows: Fa,, = 0.85 V, VINH = 2.35 V; CS = WR = RD = RESET (AD7775 only) = A0, A1 (AD7773 only) = VIN“; ALE
(AD7775 Only) = CTRL = Voay, CLKIN = 6.67 MHz at 50% Mark-Space ratio between Fa, & VIN”; no conversion in progress and data bus, DBW-DB9
(AD7773 Only), AD6-DB9 (AD7775 only), tied to 0 V. - _ -
'Input signal levels are as follows: Vrss. = 0 V, VIN“ = Vcc; cs = WR = RD = RESET (AD7775 only) = A0, A1 (AD7773 Only) - VIN"; ALE (AD7775
only) = CTRL = CLKIN = VWL; data bus, DBO-DB9 (AD7773 only), ADO-AD9 (AD7775 only) tied to 0 V.
°For capacitive loads greater than 100 pF a series resistor is required.
Specifications subject to change without notice.
REV. A
AD7773/AD7775
INTERFACE TIMING iyygthirmtisrityr--Nm731, 2 (llee = +5 ll . 5%; m = ncun = w
Limit at
Parameter Label TMIN, TMAX Units Test Conditions/Comments
INTERFACE TIMING
Address Setup to W or E6 Falling Edge t1 4 ns min
Address Hold after iWt or E Rising Edge t2 0 ns min
Address Setup to c-s F alling Edge ts 9 ns min
-igtlt or W Rising Edge to cs Rising Edge t4 0 ns min
W or E Pulse Width ts 53 ns min
TS or E Active to Valid Data3 t6 60 ns max Timed from Whichever Occurs Last
Bus Relinquish Time after Ery t7 10 ns min
22 ns max
Data Valid to wrt Rising Edge te 55 ns min
Data Valid after W Rising Edge t9 10 ns min
Delay Time Between Stack Reads tu, 100 ns min See Figure 12b
‘See Figures 1 and 2.
2Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified
with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
'ts is measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.4 V.
h, is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured time is then extrapo-
lated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t7 quoted above is the true bus relinquish time of
the device and, as such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.
AO-AI X i
A t1 t2 " t2
+13 +14 ->H
- L, t - b----, -----F
an 5 wn ti
Ath-A1
- = - 7 tr ts V t‘ -.,'.- tg
DBty-DB9 ----( [--- 080-039 -----H )--
Figure 1. Read Cycle Timing for AD7773 Interface Figure 2. Write Cycle Timing for AD7773 Interface
Figure 3. Load Circuit for Bus Timing Characteristics
-4- REV. A
