AD776AQ ,16 Bit kSPS Oversampling ADCapplications. Third order noise shaping is
employed using 64 times oversampling to provide 90 dB S ..
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10-Bit, 3 us ADC
Two DACs with Output Amplifiers
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AD7776AR ,LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCsspecifications T to T unless otherwise noted.)REFIN MIN MAX1Parameter A Versions Units Conditions/C ..
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ADM1810-10ART-RL7 ,Microprocessor Reset CircuitsaMicroprocessor Reset CircuitsADM1810–ADM1813/ADM1815–ADM1818
ADM1810-5AKS-RL7 , Microprocessor Reset Circuits
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ADM1811-5ART-REEL7 , Microprocessor Reset Circuits
ADM1811-5ART-REEL7 , Microprocessor Reset Circuits
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AD776AQ
16 Bit kSPS Oversampling ADC
ANALOG
DEVICES
16-Bit100 kSPS
Oversampling ADC
FEATURES
Monolithic 16-Bit Sigma-Delta ADC
Third-Order Noise Shaping
96 dB Dynamic Range
90 dB SNR
16-Bit 100 kHz Output from FIR Filter
12-8it 400 kHz Output from Comb Filter
No Missing Codes
<0.001 dB ln-Band Ripple
APPLICATIONS
Digital Audio Disk/Tape
Voice Bandwidth Communications
ADC Support for ADSP-21XX
High Accuracy Measurement Systems
PRODUCT DESCRIPTION
The AD776 is a 16-bit sigma-delta oversampled ADC, incorpo-
rating a l-bit third-order modulator and digital decimation filter.
An on-chip voltage reference circuit is also included.
The AD776 does not generally require the use of sample-hold
circuits or complex antialiasing filters as a result of its sigma-
delta architecture. The output is available both before and after
the final Finite Impulse Response (FIR) decimation filter. This
provides the flexibility of optimizing conversion speed or dy-
namic range: 12-bit/400 kHz (from the comb filter) or l6-bit/
100 kHz (from the FIR filter). The serial port provides easy
interface with a variety of standard processors including the
ADSP-21XX.
The AD776 is specified for ac (or "dynamic") parameters such
as SNR, THD and IMD which are important in signal process-
ing and audio applications. Third order noise shaping is
employed using 64 times oversampling to provide 90 dB SNR
and - 100 dB peak spurious component for signal bandwidths
up to 45 kHz.
The AD776 operates from a single +5 V supply and typically
consumes 350 mW during conversion. The device is packaged
in 20-pin ceramic DIP (cerdip) and is offered in an industrial
temperature grade (-4(rC to +85°C).
REV. A
III Cllhhlalhrl0 DUHBEBU HUI: cn
FUNCTIONAL BLOCK DIAGRAM
Avon DVDD rsgt
ANALOG
,__5 l
15:1 1:1
DECIMATION OECIMATION
u SERIAL
rm _’ u INTERFACE
FILTER FILTER X
ll _ 1 ll
3.2MHt
64M)" 612MHz t2aro"
SYSTEM TIMING AND CONTROL
"s1.f ter'
PRODUCT HIGHLIGHTS
l, Analog Front End. The analog input is differential providing
increased signal swing, increased power supply rejection
ratio, and reduced sensitivity to clock jitter. Since the input
signal is oversampled by a factor of 64, a complex anti-
aliasing filter is not needed,
2. Flexible Digital Interface. The AD776 has three output pins
for the serial interface: 1) serial data out (DOUT), 2) frame
sync out (FSO), and 3) serial clock out (DOUT CLOCK).
The serial port can interface with general purpose DSPs such
as the ADSP-21XX, TMS320XX, and DSP56001/2 without
additional "glue" logic.
3. Inherently Self-Sampling. The AD776 needs no external
sample-and-hold amplifier to capture and freeze the analog
input while the conversion takes place.
4. Speed/Performance Options, In addition to the standard
16-bit resolution at 100 kHz, the output of the comb filter
can be accessed to provide 12-bit resolution at 400 kHz.
ANALOG-TO-DIGITAL CONVERTERS 2-303
Jllm8--SMlFliW'll01G (ho m
m: Avon, nvm, = +5 ll , FIR filter output mode unless otherwise noted)
in Typ Max
Parameter M Units
RESOLUTION 16 Bits
TEMPERATURE RANGE -40 +85 °C
TOTAL HARMONIC DISTORTION (THD)" J. , -80 -83 dB
0.01 0.003 o/o
SIGNAL-TO-NOISE RATIO (SNR)" 3, fs = 48 ksps 88 90 dB
Signal to Noise Ratio (SNR)" 3, fs = 100 ksps 86 dB
Comb Filter Mode, CLKIN = 12.8 MHz 72 dB
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT - 100 dB
INTERMODULATION DISTORTION (IMD)"
2nd Order Products - 102 dB
3rd Order Products -98 dB
VOLTAGE REFERENCE OUTPUT (VREF) (AvDD X 0.4) - 4% AK,,, x 0.4 V (AVDD X 0.4) + 4% V
MAXIMUM ANALOG INPUT RANGES 2 x VREF - 0.5 V Tr-p
MAXIMUM INPUT SiGNAL" 20.5 VREF V p-p
DC ACCURACY'
Differential Nonlinearity :05 LSB
INL 2 LSB
Gain Error 10 %
Midscale Error 0.5 o/r
DIGITAL FILTER CHARACTERISTICS
Passband Ripple 0.001 dB
Stopband Attenuation -S)6 dB
POWER SUPPLY REQUIREMENTS
Analog Supply Voltage (AVDD) 4.5 5.0 5.5 V
Digital Supply Voltage (DVDD) 4.5 AVDD V
Analog Supply Current 20 mA
Digital Supply Current 20 mA
Power Consumption' 300 400 mW
Power Supply Rejection9 70 dB .
Parameter Test Conditions Min Typ _ Max Units
LOGIC INPUTS
V", High Level Input Vo'ltage 2.0 FL, V
Vu, Low Level Input Voltage -0.5 0.8 V
lu, High Level Input Current Vm = V m, 1 WA
In_ Low Level Input Current Vir, = 0 V . 1 “A
Cm Input Capacitance 1 10 pF
I, Hi-Z Input Current for SDO l 10 wA
LOGIC OUTPUTS f
Vos, High Level Output Voltage lor: = 0.4 mA 2.4 V
VOL Low Level Output Voltage lor, = 2.0 mA 1 0.5 V
At ,-25''C.
2Analog Input = L V rms (it 10 kHz, VLOMMON .wmr = 2.5 V,C1.K1.\' = 6.4 MHz.
‘THD performance can be improved, depending upon the application, by makum slight adjustments to the dc common mode voltage at the analog inputs.
"IMD measured at f, = 48 kHz and using 61.6 Hz and 986.4 Hz as the input tones(sum of the two peaks added to be -3 dB FS),
SApplied differentially between AIN+ and AIN-.
6The input signal may be centered at any choice of dc offset voltage as long as peak values are bounded by the Maximum Analog Input Range value. Performance may be
improved by reducing the maximum input signal by 3 dB, For nominal operation, 2.5 V dc offset is recommended.
'The A0776 may be operated from a single -5 V supply.
“AVDD, DVrora = 5.5 v; f = 12.3 MHz; T, - +85“C.
9With external voltage reference.
Specifications subicct to change without notice,
2- 104 ANALOG-TO-DIGITAL CONVERTERS
El 0811:1600 000326]: 3112 ©
REV. A
TIMING CHARACTERISTICS (NIO, i1lltn = +5 ll t 10%, u, to Tm) - see Figures 14 through 18.
Symbol Parameter Min Max Units
f Clock in Frequency 1 12.8 MHz
[CL]: Clock in Period (= 1/0 78 1000 ns
to Duty Cycle 0.475 [cm 0.525 [cm ns
ku, Clock LOW 37 41 ns' 2
475 525 as2
tcs, Clock HIGH 37 41 nsl
475 525 n52
(R Rise Time ' 5 ns
te Fall Time 5 ns
IFSS . Frame Sync Input Setup Time 20 78 ns
tFSH Frame Sync Input Hold Time 20 _, ns
[FSIL Frame Sync Input LOW 2 tern:
tooo Data Output Clock Delay 25 75 ns
toor, Data Output Clock Period 156 1115” 4
312 _nsl' 5
TFsosc FSO Setup Time Before CLKIN 130 ms
[FSOHC FSO Hold Time After CLKIN 130 ns5
thosu FSO Setup Time Before DOUT CLK 110 ns5
IFSOHD FSO HIGH to DOUT CLK Rising Edge 110 ns'
tro F SI to FSO Delay 1 tcu<4
5 tCLKS
tosu Data Output Setup Time 40 mf
130 ms
hor, Data Output Hold Time 40 ns4
130 nss
too Data Delay Time 0 20 ns
tor; 1 Data F loat Time 0 20 ns
'CLKIN = 12.8 MHz.
'CLKIN = 1 MHz.
TSI must be deasserted for at least two CLKIN periods prior to being asserted.
"Comb Filter mode.
'FIR Filter mode.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may
AVDD to AGND .................. -0.3 V to +7.0 V f"". permanent. damage to Fhe device. This is a stress. hating only and
DVDD to DGND pr..............-. _ 0.3 V to +7.0 V funeuonal eperanon of the device a) these or eny other co.nditlorts aboye those
indicated m the operational section of this specification 15 not implied.
AGND to DGND . . . . . . . . . . . . . ' . . . . _ . . . . ' t0.3 V Exposure to absolute maximum rating conditions for extended periods may
Digital Inputs t0 DGND ............. --0.3 V to DVDD affect device reliability.
Analog Inputs to AGND .............. -0.3 V to AVDD
REFIN to AGND ................. -0.3 V to +2.5 V
Soldering (.10 sec) ......................... +300°C
Storage Temperature ..... ' ........... --55°C to +150°C
CAUTION
The AD776 features input protection circuitry consisting of large "distributed" diodes and polysili-
con series resistors to dissipate both high energy discharges (Human Body Model) and fast, low
energy pulses (Charged Device Model): Per Method 3015.2 of MIL-STD-MBC, the AD776 has been
classified as a Category 1 Device. ililaIWIBl
Proper ESD precautions are strongly recommended to avoid functional damage or performance sitiiii-iiiiiitiiititit:i
degradation; Charges 'ls. high as 40.00 volts reyi.ily.accumula.te on thehuman bo.dy and test equip-
ment, and discharge without detection. Unused devices must be stored 1n conductive foam or shunts,
and the foam discharged to the destination socket before devices are removed. For further informa-
tion on ESD precaution, refer to Analog Devices' ESD Prevention Manual.
REV. A ANALOG-TO-DIGITAL CONVERTERS 2-105
© 061.121.1013 UUHBEBB i8H III
AD776 PIN DESCRIPTION
Symbol Pin Number Type Name and Function
AGND 1 Analog Ground. Return current for analog front end. No internal connection to DGND.
AIN+ 2 I Analog Signal Input. Noninverting terminal.
AIN- 3 I Analog Signal Input. Inverting terminal.
CLKIN 4 I Clock In. This T TL compatible input accepts clock frequencies in the range of
1.0 MHz-12.8 MHz, with the output sample rate of the AD776 equal to CLKIN
divided by 128 in FIR filter mode and 32 in comb filter mode.
FSI 5 I Frame Sync Input. FSI is an optional control pin used to synchronize internal
circuits and to start or reset the serial output data. If FSI is grounded, frame syncs
will be automatically generated internally. When F SI is brought HIGH, serial data
is presented at the output (DOUT-pin ll), The purpose of FSI is to control
externally the phasing of the A/D conversion process. FSI should be a periodic
signal occurring every 16 DOUT CLK clock cycles in the 12-bit/400 kHz mode and
every 32 DOUT CLK clock cycles in the 16-bit/ 100 kHz mode. When utilized,
FSI must be synchronized to CLKIN as defined in the timing specification (see
Figure 17). FSI allows multiple AD776s to be synchronized using a common frame
sync source, requiring a common CLKIN signal.
FSEL 6 1 Filter Select. FSEL - "O'' selects FIR output. FSEL = "l" selects comb filter output.
SF 7 I Serial Format. Selects output format of DOUT and FSO when FSEL = "O."
See Figures 14b and 15b.
DVDD 8 +5 V :10%. Digital Power Supply.
FSO 9 0 Frame Sync Output. Indicates beginning of serial data transmission on DOUT.
See Timing Diagrams.
DOUT CLK 10 C) Serial Data Clock. See Figures Ma and 14b. In the FIR filter output mode
(FSEL = 0), DOUT CLK is CLKIN divided by four; in the comb fitter output
mode (FSEL = 1), DOUT CLK is CLKIN divided by two.
DOUT ll 0 Data Output. Serial data is transmitted MSB first, twos complement format,
once per F so cycle with the data synchronous with DOUT CLK.
DOE 12 I Data Output Enable. Serial data (Pin ll) is an active output when DOE = "O."
Serial data is three stated when DOE = "''1.''
DGND 13 Digital Ground. Return current for digital circuitry and pad drivers.
TP3, TP, TP1,TPO 14, 15, 16, 17 Test Points. These pins must be connected to DGND.
AVDD 18 +5 V :10%. Analog Power Supply.
REFOUT 19 C) Internal Reference Output. Nominally +2 V with Ara, = +5.0 V.
REFIN 20 I Reference Input. +2 V maximum.
I = input
o = Output
PIN CONFIGURATION ORDERING GUIDE
Temperature Package Package
Am” i: . 'ss...,,)" 20 REFIN Model Range Description Option'
Am+EE 19 REFOUT ADTMAQ -4irCtof850C 20-PinCerdip Q-20
AIN- E 18 AV on *For outline information see Package Information section.
CLKIN E " TPO
F5: E 16 TP1
TOP VIEW
FSEL E (Nona Scale) 15 Tpit
SF l: 14 193
0qu E " DGND
FSO E 12 a
DOUT CLK 10 11 DOUT
2-106 ANALOG-TO-DIGITAL CONVERTERS REV. A
© 1381112600 DUHBBBB L15 III
