AD7769AN-AD7769JN-AD7769JP Fast Delivery |IC PHOENIX CO.,LIMITED

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AD7769AN-AD7769JN-AD7769JP
LC2MOS Analog I/O Port
REV.ALC2MOS
Analog I/O Port
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTSTwo-Channel, 8-Bit Analog I/O port on a Single Chip.
The AD7769 contains a two-channel, high speed ADC with
input signal conditioning and two, fast settling 8-bit DACs
with output amplifiers, on a single chip.Independent Control of Span and Offset.
The input voltage span of the ADC and the midpoint of the
transfer function, the output voltage swing of the two DACs
and the half-scale output voltage, can be set independently
by applying ground referenced control voltages.Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7769 is specified with ac parameters including signal-
to-noise ratio, distortion and signal bandwidth.Fast Microprocessor Interface.
The AD7769 has bus interface timing compatible with all
modern microprocessors, with bus access and relinquish
times less than 65 ns and a Write pulse width less than 90 ns.
FEATURES
Two-Channel, 8-Bit 2.5 ms ADC
Two 8-Bit, 2.5 ms DACs with Output Amplifiers
Span and Offset of ADC and DAC
Independently Adjustable
Low Power
APPLICATIONS
Winchester Disk Servo Controllers
Floppy Disk Microstepping
Closed Loop Servo Systems
GENERAL DESCRIPTION
The AD7769 is a complete, two-channel, 8-bit, analog I/O port.
It has versatile input and output signal conditioning features
that make it ideal for use in head-positioning servos in Winches-
ter disk systems. It is equally suitable for floppy disk microstep-
ping head positioning, other closed loop digital servo systems
and general purpose 8-bit data acquisition.
The AD7769 contains a high speed successive approximation
ADC, preceded by a two-channel multiplexer and signal condi-
tioning circuits. The input span of the ADC and the offset of
the zero point from ground can be independently set by apply-
ing ground referenced voltages. The AD7769 also contains two
independent, fast settling, 8-bit DACs with output amplifiers.
The output span and offset voltage of the DACs can be set inde-
pendently of those of the ADC. This makes the AD7769 espe-
cially useful in disk drives, where only a positive supply rail is
available and the ranges of the ADC and DACs must be refer-
enced to some positive voltage less than the supply.
The AD7769 is easily interfaced to a standard 8-bit mpu bus via
an 8-bit data port and standard microprocessor control lines.
The AD7769 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
The part is available in a 28-lead plastic DIP and 28-terminal
PLCC package.
AD7769–SPECIFICATIONS
ADC SPECIFICATIONS
(VDD = +12 V 6 10%; VCC = +5 V 6 5%; AGND [ADC] = AGND [DAC] = DGND = 0 V; VBIAS [ADC] = +5 V;
VSWING [ADC] = +2.5 V; fCLK = 5 MHz external. All specifications TMIN to TMAX1 unless otherwise noted.)
DACA, DACB SPECIFICATIONS
(VDD = +12 V 6 10%; VCC = +5 V 6 5%; AGND [DAC] = AGND [ADC] = DGND = 0 V;
VBIAS [DAC] = +5 V; VSWING [DAC] = +2.5 V; VOUTA, VOUTB load to AGND [DAC], RL = 5 kV,
CL = 100 pF. All specifications TMIN to TMAX1 unless otherwise noted.)
NOTESTemperature range as follows: J Version: 0°C to +70°C; A Version: –40°C to +85°C.
AD7769
AD7769
TIMING CHARACTERISTICS1, 2(VCC = +5 V 6 5%; VDD = +12 V 6 10%; AGND [ADC] = AGND [DAC] = DGND = 0 V.
For ADC and DAC, VBIAS = +5 V, VSWING = +2.5 V.)
NOTESSee Figures 11, 12 and 13.Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t10 and t13 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t14 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Figure 1. Load Circuits for Data Access Time TestFigure 2. Load Circuits for Bus Relinquish Time Test
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND or DGND . . . . . . . . . . . . . . . . .–0.3 V, +15 V
VCC to DGND . . . . . . . . . . . . . . . .–0.3 V, VDD +0.3 V or 7 V
(Whichever is Lower)
AGND to DGND . . . . . . . . . . . . . . . . . .–0.3 V, VDD +0.3 V
Digital Inputs to DGND
(Pins 12, 13, 15–18) . . . . . . . . . . . . . .–0.3 V, VDD +0.3 V
Digital Outputs to DGND
(Pins 3–10, 11) . . . . . . . . . . . . . . . . . . .–0.3 V, VCC +0.3 V
Analog Inputs to AGND . . . . . . . . . . . . .–0.3 V, VDD +0.3 V
Analog Outputs to AGND . . . . . . . . . . . .–0.3 V, VDD +0.3 V
Operating Temperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . .0°C to +70°C
Industrial (A Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Power Dissipation (Any Package)
to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500 mW
Derates Above +75°C by . . . . . . . . . . . . . . . . . . .6 mW/°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering 10 secs) . . . . . . . . . . . .+300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7769 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
*N = Plastic DIP; P = Plastic Leaded Chip Carrier.
NOTE
Do not allow VCC to exceed VDD by more than 0.3 V. In cases
where this can happen the diode protection scheme shown
below is recommended.
PIN CONFIGURATIONS
DIPPLCC
AD7769
PIN FUNCTION DESCRIPTION
TERMINOLOGY
Relative Accuracy
For an ADC, Relative Accuracy or endpoint nonlinearity is the
maximum deviation, in LSBs, of the ADC’s actual code transi-
tion points from a straight line drawn between the endpoints of
the ADC transfer function, i.e., the 00 to 01 and FE to FF Hex
(01111111 to 11111111 Binary) code transitions.
For a DAC, Relative Accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func-
tion, i.e., those voltages which correspond to codes 00 and FF
Hex.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max en-
sures monotonicity (DAC) or no missed codes (ADC).
Bias Offset Error
For an ideal ADC, the output code for an input voltage equal to
VBIAS (ADC), should be 80 Hex (10000000 binary). The ADC
Bias Offset Error is the difference between the actual midpoint
voltage for code 80 Hex and VBIAS (ADC), expressed in LSBs.
For an ideal DAC, the output voltage for code 80 Hex should
Plus and Minus Full-Scale Error
The ADC and DACs in the AD7769 can be considered as de-
vices with bipolar (plus and minus) input ranges, but referred to
VBIAS instead of AGND. Plus Full-Scale Error for the ADC is the
difference between the actual input voltage at the FE to FF code
transition and the ideal input voltage (VBIAS + VSWING –1.5 LSB),
expressed in LSBs. Minus Full-Scale Error is similarly specified
for the 01 to 00 code transition, relative to the ideal input voltage
for this transition (VBIAS – VSWING +0.5 LSB). Plus Full-Scale
Error for the DACs is the difference, expressed in LSBs, between
the actual output voltage for input code FF and the ideal voltage
(VBIAS + VSWING – 1 LSB). Minus Full-Scale Error is similarly
specified for code 00, relative to the ideal output voltage (VBIAS –
VSWING). Note that Plus and Minus Full-Scale errors for the
ADC and the DAC outputs are measured after their respective
Bias Offset errors have been adjusted out.
Digital-to-Analog Glitch Impulse
Digital-to-Analog Glitch Impulse is the impulse injected into the
analog outputs when the digital inputs change state with either
DAC selected. It is normally specified as the area of the glitch in
nV secs and is measured when the digital input code is changed
by 1 LSB at the major carry transition.
Digital Feedthrough
Digital Feedthrough is also a measure of the impulse injected
into the analog outputs from the digital inputs but is measured
when the DACs are not selected. This is essentially feedthrough
across the die and package. It is important in the AD7769 since
it is a measure of the glitch impulse transferred to the analog
outputs when data is read from the ADC register. It is specified
in nV secs and measured with WR high and a digital code
change from all 0s to all 1s.
Signal-to-Noise Ratio (SNR)
SNR is the measured Signal-to-Noise Ratio at the output of the
converter. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency. SNR is dependent on the number
of quantization levels used in the digitization process; the more
levels, the smaller the quantization noise. The theoretical SNR
for a sine wave is given by
SNR = (6.02N + 1.76) dB
where N is the number of bits. Thus for an ideal 8-bit converter,
SNR = 49.92 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamen-
tal. For the AD7769, Total Harmonic Distortion is defined as
20 log
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the individual
harmonics.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products, of order (m+n), at sum and difference frequencies of
mfa+nfb, where m, n = 0, 1, 2, 3 . . . Intermodulation terms are
those for which neither m nor n is equal to zero. For example,
the second order terms include (fa+fb) and (fa–fb) and the third
order terms include (2fa+fb), (2fa–fb), (fa+2fb) and (fa–2fb).
LOGIC TRUTH TABLE
ADC CHANNEL SELECT AND START CONVERSION
READ ADC DATA
WRITE TO DACA OR DACB
NOTESIf RD = 1, DB0–DB7 will remain high impedance. If RD = 0, DB0–DB7 will output previous ADC data. The RD input should not change during a conversion.X = Don’t Care.N/C = No Change.
AD7769
CIRCUIT DESCRIPTION
Analog Inputs and Outputs
The AD7769 provides the analog-to-digital and digital-to-analog
conversion functions required between the microcontroller and
the servo power amplifier in digital servo systems. It is intended
primarily for closed loop head positioning in Winchester disk
drives, but may also be used for microstepping in drives with
stepper motor head positioning or other servo applications. The
AD7769 contains a high speed, 8-bit, sampling ADC with two
input channels and two 8-bit DACs with output buffer amplifi-
ers. A unique feature of the AD7769 is the input and output sig-
nal conditioning circuitry that allows the analog input and
output voltages to be referred to a point other than analog
ground. The input range and offset of the ADC, the output
swing and offset of the DACs may be adjusted independently by
the application of ground-referenced, positive control voltages,
VBIAS (ADC), VSWING (ADC), VBIAS (DAC) and VSWING (DAC).
Thus, for example, the peak-to-peak output swing of the DACs
could be set to 3 V above and 3 V below a bias voltage of 5 V.
Figures 5 and 6 show the transfer functions of the ADC
and DACs and their relationship to VBIAS and VSWING. The
Figure 5.ADC Transfer Function
midpoint code of the ADC, 80 Hex (10000000 Binary), occurs
at an input voltage equal to VBIAS. The input FSR of the ADC is
equal to 2 VSWING, so that the Plus Full-Scale code transition
(FE to FF Hex) occurs at a voltage equal to VBIAS + VSWING
–1.5 LSBs and the Minus Full-Scale code transition (01 to 00
Hex) occurs at a voltage VBIAS – VSWING +0.5 LSBs. The
transfer function of the DACs bears a similar relationship to
VBIAS and VSWING. The DAC output voltage for code 80 Hex
(10000000 binary) is equal to VBIAS, while FF Hex (11111111
binary) gives an output voltage of VBIAS + VSWING –1 LSB
(Plus Full-Scale) and 00 Hex gives an output voltage of VBIAS –
VSWING (Minus Full-Scale).
The ability to refer input and output signals to some voltage
other than ground is of particular importance in disk drive ap-
plications. Typically, only +5 V digital and +12 V analog supply
voltages are available, and the analog signals are often referred
to a voltage around half the analog supply.
Driving the Analog Inputs and Reference Inputs
The analog inputs, VINA and VINB, must be driven from low
output impedance sources, such as from op amps. In addition,
VBIAS (ADC) must be driven from a similar type low impedance
source (e.g., voltage reference).
Op amps are not required to drive the VSWING (ADC), VBIAS
(DAC) and VSWING (DAC) inputs as these are high impedance
inputs (200 nA typical input current) that feed into on-chip
buffer amplifiers. The reference voltages for these inputs can be
derived using suitable resistor divider networks.
The analog reference available in the disk drive system can be
used to set the bias voltage of the AD7769, and could also be at-
tenuated to provide the reference for the input and output swing
as shown in Figure 7. The same bias voltage would generally
(though not necessarily) be used for the ADC and the DACs,
though the input and output ranges might be different.
Figure 7.Typical Analog Connections to the AD7769
ADC Conversion Cycle
Figure 8 shows the operating waveforms for a conversion cycle.
On the rising edge of WR, the conversion cycle starts with the
acquisition and tracking of the selected ADC channel, VINA or
VINB. The analog input voltage is held 50 ns (typically) after the
fourth falling edge of the input CLK following a conversion
start. If tD in Figure 8 is greater than 150 ns, then the falling

Partno	Mfg	Dc	Qty	Available	Descript
AD7769AN		N/a	11	avai	LC2MOS Analog I/O Port
AD7769JN	AD	N/a	12	avai	LC2MOS Analog I/O Port
AD7769JP		N/a	900	avai	LC2MOS Analog I/O Port