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AD7760BSV
2.5 MSPS, 20-Bit ADC
2.5 MSPS, 20-Bit Σ∆ ADCRev. PrN
FEATURES
High performance 20-bit Sigma-Delta ADC
118dB SNR at 78kHz output data rate
100dB SNR at 2.5MHz output data rate
2.5 MHz maximum fully filtered output word rate
Programmable over-sampling rate (8x to 256x)
Flexible parallel interface
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low pass FIR filter with default or user programmable
coefficients
Over-range alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power down modes
Synchronization of multiple devices via SYNC pin
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DB0 - DB15
VIN+VIN-
AVDD1
AGND
VREF+
MCLK
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DRD
DGND
VDRIVE
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AVDD2
AVDD3
AVDD4
DVDD
DECAP
RBIASFigure 1.
PRODUCT OVERVIEW The AD7760 high performance 20-bit sigma delta analog to
digital converter combines wide input bandwidth and high
speed with the benefits of sigma delta conversion with
performance of 100dB SNR at 2.5MSPS making it ideal for high
speed data acquisition. Wide dynamic range combined with
significantly reduced anti-aliasing requirements simplify the
design process. An integrated buffer to drive the reference, a
differential amplifier for signal buffering and level shifting, an
over-range flag, internal gain & offset registers and a low-pass
digital FIR filter make the AD7760 a compact highly integrated
data acquisition device requiring minimal peripheral
component selection. In addition the device offers
programmable decimation rates and the digital FIR filter can be
adjusted if the default characteristics are not appropriate to the
application. The AD7760 is ideal for applications demanding
high SNR without necessitating design of complex front end
signal processing.
The differential input is sampled at up to 40MS/s by an analog
modulator. The modulator output is processed by a series of
low-pass filters, the final one having default or user
programmable coefficients. The sample rate, filter corner
frequencies and output word rate are set by a combination of
the external clock frequency and the configuration registers of
the AD7760.
The reference voltage supplied to the AD7760 determines the
analog input range. With a 4V reference, the analog input range
is ±3.2V differential biased around a common mode of 2V. This
common mode biasing can be achieved using the on-chip
differential amplifiers, further reducing the external signal
conditioning requirements.
The AD7760 is available in an exposed paddle 64-lead TQFP
and 48-lead CSP packages and is specified over the industrial
temperature range from -40°C to +85°C.
TABLE OF CONTENTS TABLE OF CONTENTS..................................................................2
AD7760—Specifications..................................................................3
Timing Specifications.......................................................................5
Timing Diagrams..............................................................................6
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Functional Descriptions..........................8
Terminology....................................................................................10
Typical Performance Characteristics...........................................11
Theory of Operation......................................................................12
AD7760 Interface............................................................................13
Clocking the AD7760.....................................................................14
Driving The AD7760......................................................................15
Using The AD7760.....................................................................16
Bias Resistor Selection...............................................................16
Programmable FIR Filter...............................................................17
Downloading a User-Defined Filter............................................18
Example Filter Download.........................................................18
AD7760 Registers...........................................................................20
Non Bit-Mapped Registers........................................................21
Outline Dimensions.......................................................................22
Ordering Guide..........................................................................22
REVISION HISTORY AD7760—SPECIFICATIONS
Table 1. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, TA = +25°C, Full Power Mode, unless otherwise noted
See Terminology
TIMING SPECIFICATIONS
Table 2. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, VDRIVE = TBD V, TA = +25°C, CLOAD = 25pF, Full Power Mode, unless otherwise noted
1 tICLK = 1/fICLK
TIMING DIAGRAMS ��
Figure 2. Parallel Interface Timing Diagram
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Figure 3. 20MHz Modulator Data Output Mode
Figure 4. AD7760 Register Write
ABSOLUTE MAXIMUM RATINGS
Table 3. TA = 25°C, unless otherwise noted. 1Transient currents of up to TBD mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
DB8DB9DB10DB11
DECAP2DECAP3
AGNDAGND
AGND
AVDD2
AVDD2
AGND
DB12
DB13
DB14
DB15
VDRIVE
DGND
DGND
DVDD
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DGND
AGND
AVDD1
BIAS
AGND
A1+
A1-
OUT
A1-
OUT
A1+
AGND
DD3
DD2
AGND
DRIVE
DGNDDGNDDB0DB1DB2DB3DB4DB5DB6DB7DGND
DGND
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MCLK
AVDD2
AVDD1
AGND
VREF+
AGND
AVDD4
AGND
DECAP1
REFGNDFigure 5. 64-Lead TQFP Pin Configuration
DB15
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AD7760
TOP VIEW
(Not to Scale)
VDRIVE
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MCLK
AVDD2
AVDD1
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REFGND
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AVDD4
AVDD2
AVDD2
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DD3
DD2
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AVDD1
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DVDD
VDRIVE
DB14
DB13
DB12
DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
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Table 4. Pin Function Descriptions TERMINOLOGY
Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by dBNDistortiontoSignal76.102.+=+
Thus, for an 18-bit converter, this is 110.12dBs and for a 20-bit
converter, 122.16 dB.
Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For
the AD7760, it is defined as 20dBTHD=log
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the
sixth harmonics.
Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but, for ADCs where the harmonics are buried in the
noise floor, it is a noise peak.
Non-Harmonic Spurious Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component excluding harmonics.
Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa
− 2fb).
The AD7760 is tested using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dB.
Integral Nonlinearity (INL) The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error The deviation of the first code transition (000...000 to 000...001)
from the ideal (that is, AGND + 1 LSB).
Gain Error The deviation of the last code transition (111...110 to 111...111)
from the ideal (that is, VREF − 1 LSB), after the offset error has
been adjusted out.
Power Supply Rejection Ratio (PSRR) The ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 100 mV p-p sine wave applied to
the ADC VDD supply of frequency fs. The frequency of this
input varies from 1 kHz to 1 MHz. )PfsPSRRlog10
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: TA = 25°C, TBD, unless otherwise noted.
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