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AD775JN-AD775JR
8-Bit 20 MSPS, 60 mW Sampling A/D Converter
REV.0
8-Bit 20 MSPS, 60 mW
Sampling A/D Converter
FEATURES
CMOS 8-Bit 20 MSPS Sampling A/D Converter
Low Power Dissipation: 60 mW
+5 V Single Supply Operation
Differential Nonlinearity: 0.3 LSB
Differential Gain: 1%
Differential Phase: 0.5 Degrees
Three-State Outputs
On-Chip Reference Bias Resistors
Adjustable Reference Input
Video Industry Standard Pinout
Small Packages:
24-Pin 300 Mil SOIC Surface Mount
24-Pin 400 Mil Plastic DIP
PRODUCT DESCRIPTIONThe AD775 is a CMOS, low power, 8-bit, 20 MSPS sampling
analog-to-digital converter (ADC). The AD775 features a built-
in sampling function and on-chip reference bias resistors to pro-
vide a complete 8-bit ADC solution. The AD775 utilizes a
pipelined/ping pong two-step flash architecture to provide high
sampling rates (up to 35 MHz) while maintaining very low
power consumption (60 mW).
Its combination of excellent DNL, fast sampling rate, low dif-
ferential gain and phase errors, extremely low power dissipation,
and single +5 V supply operation make it ideally suited for a
variety of video and image acquisition applications, including
portable equipment. The AD775’s reference ladder may be con-
nected in a variety of configurations to accommodate different
input ranges. The low input capacitance (11 pF typical) provides
an easy-to-drive input load compared to conventional flash
converters.
The AD775 is offered in both 300 mil SOIC and 400 mil DIP
plastic packages, and is designed to operate over an extended
commercial temperature range (–20°C to +75°C).
AD775–SPECIFICATIONSVIDEO ACCURACY
ANALOG INPUT
AC SPECIFICATIONS
NOTESNSTC 40 IRE modulation ramp, CLOCK = 14.3 MSPS.fIN amplitude = 0.3 dB full scale.
Specifications subject to change without notice. See Definition of Specifications for additional information.
(TA = +258C with AVDD, DVDD = +5 V, AVSS, DVSS = 0 V, VRT = 2.6 V, VRB = +0.6 V,
CLOCK = 20 MHz unless otherwise noted)
AD775DIGITAL SPECIFICATIONSLOGIC OUTPUTS
TIMING SPECIFICATIONSPipeline Delay (Latency)
Sampling Delay
Specifications subject to change without notice.
VIN
CLK
OUT
DATA N-3DATA N-2DATA N-1DATA N
tODFigure 1.AD775 Timing Diagram
(TA = +258C with AVDD, DVDD = +5 V, AVSS, DVSS = 0 V, VRT = 2.6 V, VRB = +0.6 V,
CLOCK = 20 MHz unless otherwise noted)
Figure 5.
(VIN = –0.3 dB)
Figure 6.
(VIN = –0.5 dB)
Figure 2.S/(N + D) vs. Input Frequency at 20 MSPS Clock
Rate (VIN = –0.3 dB)
FREQUENCY – MHzFigure 3.Typical FFT at 1 MHz Input, 20 MSPS Clock Rate
(VIN = –0.5 dB)
+0.4
+FULLSCALE
–FULLSCALE
+0.1
+0.2
+0.3
DNL – LSBFigure 4.Typical Differential Nonlinearity (DNL)
AD775
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code tran-
sition. “Full scale” is defined as a level 1 1/2 LSB beyond the
last code transition. The deviation is measured from the center
of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) is guaranteed.
Offset ErrorThe first code transition should occur at a level 1/2 LSB above
nominal negative full scale. Offset referred to the Bottom of
Ladder VRB is defined as the deviation from this ideal. The last
code transition should occur 1 1/2 LSB below the nominal
positive full scale. Offset referred to the Top of Ladder VRT is
defined as the deviation from this ideal.
Differential GainThe percentage difference between the output amplitudes of a
small high frequency sine wave at two stated levels of a low fre-
quency signal on which it is superimposed.
Differential PhaseThe difference in the output phase of a small high frequency
sine wave at two stated levels of a low frequency signal on which
it is superimposed.
Pipeline Delay (Latency)The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
Signal-to-Noise Plus Distortion Ratio (S/N+D)S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components including har-
monics but excluding dc. The value for S/N+D is expressed in
decibels.
Total Harmonic Distortion (THD)THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is ex-
pressed as a percentage or in decibels.
THEORY OF OPERATIONThe AD775 uses a pipelined two-step (subranging) flash archi-
tecture to achieve significantly lower power and lower input
capacitance than conventional full flash converters while still
maintaining high throughput. The analog input is sampled by
the switched capacitor comparators on the falling edge of the
input clock: no external sample and hold is required. The coarse
comparators determine the top four bits (MSBs), and select the
appropriate reference ladder taps for the fine comparators. With
the next falling edge of the clock, the fine comparators determine
the bottom four bits (LSBs). Since the LSB comparators require
a full clock cycle between their sampling instant and their deci-
sion, the converter alternates between two sets of fine compara-
tors in a “ping-pong” fashion. This multiplexing allows a new
input sample to be taken on every falling clock edge, thereby
providing 20 MSPS operation. The data is accumulated in the
correction logic and output through a three-state output latch
on the rising edge of the clock. The latency between input sam-
pling and the corresponding converted output is 2.5 clock cycles.
All three comparator banks utilize the same resistive ladder for
their reference input. The analog input range is determined by
the voltages applied to the bottom and top of the ladder, and
the AD775 can digitize inputs down to 0 V using a single sup-
ply. On-chip application resistors are provided to allow the
ladder to be conveniently biased by the supply voltage.
The AD775 uses switched capacitor autozeroing techniques to
cancel the comparators’ offsets and achieve excellent differential
nonlinearity performance: typically ±0.3 LSB. The integral
nonlinearity is determined by the linearity of the reference lad-
APPLYING THE AD775
REFERENCE INPUTThe AD775 features a resistive reference ladder similar to that
found in most conventional flash converters. The analog input
range of the converter falls between the top (VRT) and bottom
(VRB) voltages of this ladder. The nominal resistance of the lad-
der is 300 ohms, though this may vary from 230 ohms to 450
ohms. The minimum recommended voltage for VRB is 0 V; the
linearity performance of the converter may deteriorate for input
spans (VRB–VRB) below 1.8 V. While 2.8 V is the recommended
maximum ladder top voltage (VRT), the top of the ladder may be
as high as the positive supply voltage (AVDD) with minimal lin-
earity degradation.
Figure 8.
