AD773AJD Fast Delivery |IC PHOENIX CO.,LIMITED

AD773AJD ,10-Bit, 20 MSPS Monolithic A/D ConverterSpecifications)OTRBIT 1 BIT 10MSB(MSB) (LSB)PRODUCT DESCRIPTION PRODUCT HIGHLIGHTSThe AD773A is a m ..
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ADM1181AAN ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversAPPLICATIONS12 R1 13 R1R1INOUTCMOS EIA/TIA-232General Purpose RS-232 Data LinkOUTPUTSINPUTS*R2 9 R2 ..
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AD773AJD
10-Bit, 20 MSPS Monolithic A/D Converter
FUNCTIONAL BLOCK DIAGRAM
CORRECTION LOGIC
OUTPUT BUFFERS
TIMING
CONTROL42465, 283, 2519
AD773A
REFINREFGNDAGNDDGNDDRGNDAVDDAVSSDVDDDRVDD
7, 228, 21
OTRMSB
CLOCK
VINA
VINB
BIT 1
(MSB)
BIT 10
(LSB)9
REV.010-Bit, 20 MSPS
Monolithic A/D Converter
PRODUCT DESCRIPTION
The AD773A is a monolithic 10-bit, 20 Msps analog-to-digital
converter incorporating an on-board, high performance track-
and-hold amplifier (THA). The AD773A converts video
bandwidth signals without the use of an external THA. The
AD773A implements a multistage differential pipelined
architecture with output error correction logic. The AD773A
offers accurate performance and guarantees no missing codes
over the full operating temperature range.
Output data is presented in binary and twos complement
format. An out of range (OTR) signal indicates the analog input
voltage is beyond the specified input range. OTR can be
decoded with the MSB/MSB pins to signal an underflow or
overflow condition. The high impedance reference input allows
multiple AD773As to be driven in parallel from a single
reference.
The combined dc precision and dynamic performance of the
AD773A is useful in a variety of applications. Typical
applications include: video enhancement, HDTV, ghost
cancellation, ultrasound imaging, radar and high speed data
acquisition.
The AD773A was designed using Analog Devices’ ABCMOS-1
process which utilizes high speed bipolar and 2-micron CMOS
transistors on a single chip. High speed, precision analog
circuits are now combined with high density logic circuits. Laser
trimmed thin film resistors are used to optimize accuracy and
temperature stability.
The AD773A is packaged in a 28-pin ceramic DIP and is
available in commercial (0°C to +70°C) and military (–55°C to
+125°C) grades.
FEATURES
Monolithic 10-Bit, 20 MSPS A/D Converter
Low Power Dissipation: 1.0 W
Signal-to-Noise Plus Distortion Ratio
fIN = 1 MHz: 56 dB
fIN = 10 MHz: 54 dB
Guaranteed No Missing Codes
On-Chip Track-and-Hold Amplifier
100 MHz Full Power Bandwidth
High Impedance Reference Input
Out of Range Output
Twos Complement and Binary Output Data
Available in Commercial and Military Temperature
Ranges (See Military/Aerospace Reference Manual
for Specifications)
PRODUCT HIGHLIGHTSOn-board THA
The high impedance differential input THA eliminates the
need for external buffering or sample and hold amplifiers.
The THA offers the choice of differential or single-ended
inputs. Input current is typically 5 μA.High Impedance Reference Input
The high impedance reference input (200 kΩ) allows direct
connection with standard +2.5 V references, such as the
AD680, AD580 and REF43.Output Data Flexibility
Output data is available in bipolar offset and bipolar twos
complement binary format.Out of Range (OTR)
The OTR output bit indicates when the input signal is
beyond the AD773A’s input range.Military Temperature Range
AD773A–SPECIFICATIONS
DC SPECIFICATIONS
NOTESCL = 15 pF.100% production tested.
Specifications subject to change without notice. See Definition of Specifications for additional information.
(TMIN to TMAX with AVDD = +5 V 6 5%, AVSS = –5 V 6 5%, DVDD = +5 V 6 5%,
DRVDD = +5 V 6 5%, VREF = +2.500 V unless otherwise noted)
AD773A
AC SPECIFICATIONS
NOTESFor typical dynamic performance curves at fSAMPLE = 20 Msps see Figures 2 through 7.fIN = 1 MHz.fa = 1.0 MHz, fb = 1.05 MHz.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Figure 1.AD773A Timing Diagram
(TMIN to TMAX with AVDD = +5 V 6 5%, AVSS = –5 V 6 5%, DVDD, = +5 V 6 5%, DRVDD = +5 V 6 5%,
VREF = +2.500 V unless otherwise noted, fSAMPLE = 20 MSPS, flN amplitude = –0.5 dB)
(for all grades TMIN to TMAX with AVDD = +5 V 6 5%, AVSS = –5 V 6 5%, DVDD = +5 V 6 5%,
DRVDD = +5 V 6 5%, VREF = +2.500 V unless otherwise noted, fSAMPLE = 20 MSPS)
AD773A
ORDERING GUIDE1
NOTESSee Military/Aerospace Reference Manual for AD773ASD/883B specifications.D = Ceramic DIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.
PIN CONFIGURATION
PIN DESCRIPTION
Type: AI = Analog Input; DI = Digital Input; DO = Digital
Output; P = Power.
INTEGRAL NONLINEARITY (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale.” The point
used as “zero” occurs 1/2 LSB before the first code transition.
“Full scale” is defined as a level 1 1/2 LSB beyond the last code
transition. The deviation is measured from the center of each
particular code to the true straight line.
DIFFERENTIAL LINEARITY ERROR
(DNL, NO MISSING CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value.
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below analog common. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur for an analog value
1/2 LSB above nominal negative full scale. The last transition
should occur 1 1/2 LSB below the nominal positive full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
POWER SUPPLY REJECTION
One of the effects of power supply variation on the performance
of the device will be a change in gain error. The specification
shows the maximum gain error deviation as the supplies are
varied from their nominal values to their specified limits.
SIGNAL-TO-NOISE PLUS DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components including
harmonics but excluding dc. The value for S/N+D is expressed
in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is calculated from the following expression:
S/N+D = 6.02N + 1.76, where N is equal to the effective
number of bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
SPURIOUS FREE DYNAMIC RANGE
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa±nfb,
where m, n = 0, 1, 2, 3.... Intermodulation terms are those for
which m or n is not equal to zero. For example, the second
order terms are (fa+fb) and (fa–fb) and the third order terms are
(2fa+fb), (2fa–fb), (fa+2fb) and (fa–2fb). The IMD products
are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
The two signals are of equal amplitude and the peak value of
their sums is –0.5 dB from full scale. The IMD products are
normalized to a 0 dB input signal.
DIFFERENTIAL GAIN
The percentage difference between the output amplitudes of a
small high frequency sine wave at two stated levels of a low
frequency signal on which it is superimposed.
DIFFERENTIAL PHASE
The difference in the output phase of a small high frequency
sine wave at two stated levels of a low frequency signal on which
it is superimposed.
TRANSIENT RESPONSE
The time required for the AD773A to achieve its rated accuracy
after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY TIME
The time required for the ADC to recover to full accuracy after
an analog input signal 150% of full scale is reduced to 50% of
the full-scale value.
APERTURE DELAY
The difference between the switch delay and the analog delay of
the THA. This effective delay represents the point in time,
relative to the falling edge of the CLOCK input, that the analog
input is sampled.
APERTURE JITTER
The variations in aperture delay for successive samples.
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
FULL POWER BANDWIDTH
The input frequency at which the amplitude of the reconstructed
fundamental is reduced by 3 dB for a full-scale input.
AD773A
–Dynamic Characteristics
Figure 2.S/N+D vs. Input Frequency, fCLK = 20 MSPS
Figure 3.CMR vs. Input Frequency, fCLK = 20 MSPS
FREQUENCY – Hz
AMPLITUDE – dB
1E+051E+061E+071E+081E+09
AAAAAA
Figure 4.Harmonic Distortion vs. Input Frequency,
fCLK = 20 MSPS: Full Power
Figure 5.
fCLK = 20 MSPS: Small Signal
Figure 6.
fIN = 1 MHz at 1 V p-p
Figure 7.
fIN = 9.9 MHz at 1 V p-p
Theory of Operation
The AD773A uses a pipelined multistage architecture with a
differential input, fast settling track-and-hold amplifier (THA).
Traditionally, high speed ADCs have used parallel, or flash
architectures. When compared to flash converters, multistage
architectures reduce the power dissipation and die size by
reducing the number of comparators. For example, the
AD773A uses 48 comparators compared to 1023 comparators
for a 10-bit flash architecture.
The AD773A’s main signal path transmits differential current
mode signals. Low impedance current summing techniques are
employed, increasing speed by reducing sensitivity to parasitic
capacitances. Pipelining allows the stages to operate concur-
rently and maximizes system throughput.
The input THA is followed by three 4-bit conversion stages. At
any given time, the first stage operates on the most recent sample,
while the second stage operates on a signal dependent on the
previous sample. This process continues throughout all three
stages. The twelve digital bits provided by the three 4-bit stages
are combined in the correction logic to produce a 10-bit repre-
sentation of the sampled analog input.
Pipeline delay, or latency, is four clock cycles. New output data
is provided every clock cycle and is provided in both binary and
twos complement format. The AD773A will flag an out-of-
range condition when the analog input exceeds the specified
analog input range.
Applying the AD773A
DRIVING THE AD773A INPUT
The AD773A may be driven in a single-ended or differential
fashion. VINA is the positive input, and VINB is the negative
input. In the single-ended configuration either VINA or VINB is
connected to Analog Ground (AGND) while the other input is
driven with a full-scale input of ±500 mV p-p. An inverted
mode of operation can he achieved by simply interchanging the
input connections.
Both inputs of the AD773A, VINA and VINB, are high impedance
and do not need to be driven by a low impedance source. Note,
however, that as the source impedance increases, the input node
becomes more susceptible to noise. The increased noise at the
input will degrade performance. A 10 pF capacitor across VINA
and VINB as shown in Figure 8 is recommended to bypass high
frequency noise.
VINAAD773A500mV
VINB
INPUT CONDITIONING
In some cases, it may be appropriate to buffer the input source,
add dc offset, or otherwise condition the input signal of the
AD773A. Choosing an appropriate op amp will vary with
system requirements and the desired level of performance. Some
suggested op amps are the AD9617, AD842, and AD827.
Figure 9 shows a typical application where a unipolar signal is
level shifted to the bipolar input range of the AD773A. Note
that the reference used with the AD773A can also provide a
noise-free voltage source to generate the dc offset.
Figure 9.
DIFFERENTIAL INPUT CONNECTIONS
Operating the AD773A with fully differential inputs offers the
advantage of rejecting common-mode signals present on both
VINA and VINB. The full-scale input range of VINA and VINB
when driven differentially is ±250 mV p-p as shown in Table I.
Table I. AD773A’s Maximum Differential Input Voltage
In some applications it may be desirable to convert a single-
ended signal to a differential signal before being applied to the
AD773A. Figure 10 shows a single-ended to differential video
line driver capable of driving doubly terminated cables.
AD773A
REFERENCE INPUT
The AD773A’s high impedance reference input allows direct
connection with standard voltage references. Unlike the resistor
ladder requirements of a flash converter the AD773A’s single
pin, high impedance input can be driven from one low cost, low
power reference. The high impedance input allows multiple
AD773A’s to be driven from one reference thus minimizing drift
errors.
Figure 11 shows the AD773A connected to the AD680. The
AD680 is a single supply, low power, low cost 2.5 V reference
with performance specifications ideally suited for the AD773A.
The low pass filter minimizes the AD680’s wideband noise.
Other recommended 2.5 V references are the AD580 and
REF43.
Figure 11.Recommended AD773A to AD680 Connection
CLOCK INPUT
The AD773A’s pipelined architecture operates on both the
rising and falling edges of the clock input. A low jitter,
symmetrical clock will provide the highest level of performance.
The recommended logic family to drive the clock input is HC.
The AD773A’s minimum clock half cycle may necessitate the
use of an external divide-by-two circuit as shown in Figure 12.
Power dissipation will vary with input clock frequency as shown
in Figure 13.
+5V
74XX74
40MHz
+5V
CLK
Figure 12.Divide-by-Two Clock Circuit
EQUIVALENT ANALOG INPUT CIRCUIT
The AD773A equivalent analog input circuit is shown in Figure
14. The typical input bias current is 5 μA, while input
capacitance is typically 5 pF. In the single-ended input
configuration one input is connected to AGND while the
second input is driven to full scale (±500 mV). Under nominal
conditions the collector of the input transistor is at +1.15 V.
This allows signals to be offset by up to +0.65 V without
significantly degrading performance. In the negative direction,
the emitter of the input transistor should not drop below
–1.25 V. Therefore, signals can be offset by –0.65 V without
significant performance degradation. Figure 15 shows
signal-to-noise ratio vs. common-mode input voltage.

Partno	Mfg	Dc	Qty	Available	Descript
AD773AJD	AD	N/a	2	avai	10-Bit, 20 MSPS Monolithic A/D Converter