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ADM1181AAN ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/ReceiversAPPLICATIONS12 R1 13 R1R1INOUTCMOS EIA/TIA-232General Purpose RS-232 Data LinkOUTPUTSINPUTS*R2 9 R2 ..
ADM1181AARWZ , EMI/EMC-Compliant, -15 kV, ESD-Protected RS-232 Line Drivers/Receivers
ADM1185ARMZ-1REEL7 , Quad Voltage Monitor and Sequencer
AD7738BRU
8-Channel, High Throughput,
REV.0
8-Channel, High Throughput,
24-Bit �-� ADC
FEATURES
High Resolution ADC
24 Bits No Missing Codes�0.0015% Nonlinearity
Optimized for Fast Channel Switching
18-Bits p-p Resolution (21 Bits Effective) at 500 Hz
16-Bits p-p Resolution (19 Bits Effective) at 8.5 kHz
15-Bits p-p Resolution (18 Bits Effective) at 15 kHz
On-Chip Per Channel System Calibration
Configurable Inputs
8 Single-Ended or 4 Fully Differential
Input Ranges
+625 mV, +1.25 V, +2.5 V, �625 mV, �1.25 V, �2.5 V
3-Wire Serial Interface
SPI™, QSPI™, MICROWIRE™ and DSP Compatible
Schmitt Trigger on Logic Inputs
Single-Supply Operation
5 V Analog Supply
3 V or 5 V Digital Supply
Package: 28-Lead TSSOP
APPLICATIONS
PLCs/DCS
Multiplexing Applications
Process Control
Industrial Instrumentation
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD7738 is a high precision, high throughput analog front
end. True 16-bit p-p resolution is achievable with a total con-
version time of 117 µs (8.5 kHz channel switching), making it
ideally suitable for high resolution multiplexing applications.
The part can be configured via a simple digital interface, which
allows users to balance the noise performance against data
throughput up to a 15.4 kHz.
The analog front end features eight single-ended or four fully
differential input channels with unipolar or bipolar 625 mV,
1.25 V, and 2.5 V input ranges and accepts a common-mode
input voltage from 200 mV above AGND to AVDD – 300 mV.
The multiplexer output is pinned out externally, allowing the
user to implement programmable gain or signal conditioning
before applying the input to the ADC.
The differential reference input features “No-Reference” detect
capability. The ADC also supports per channel system calibra-
tion options.
The digital serial interface can be configured for 3-wire opera-
tion and is compatible with microcontrollers and digital signal
processors. All interface inputs are Schmitt triggered.
The part is specified for operation over the extended industrial
temperature range of –40�C to +105�C.
Other parts in the AD7738 family are the AD7734 and the
AD7732.
The AD7734 analog front end features four single-ended input
channels with unipolar or true bipolar input ranges to ±10 V
while operating from a single 5 V analog supply. The AD7734
accepts an analog input overvoltage to ±16.5 V while not
degrading the performance of the adjacent channels.
The AD7732 is similar to AD7734, but its analog front end
features two fully differential input channels.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation
AD7738–SPECIFICATIONSREFERENCE INPUT
(–40�C to +105�C, AVDD = 5 V � 5%, DVDD = 2.7 V to 3.6 V or 5 V � 5%,
REFIN(+) = 2.5 V, REFIN(–) = 0 V, AINCOM = 2.5 V, MUXOUT(+) = ADCIN(+), MUXOUT(–) = ADCIN(–), Internal Buffer ON, AIN Range = �1.25 V,
fMCLK = 6.144 MHz; unless otherwise noted.)
AD7738POWER REQUIREMENTS
NOTES
1Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release.
2Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise.
3Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error.
4Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise.
5The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max.
Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the
Mode register. See the register description and circuit description for more details.
6If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins,
and any additional capacitance connected to the MUXOUT. See the circuit description for more details.
7For specified performance. Part is functional with Lower VREF
8Dynamic current charging the sigma-delta modulator input switching capacitor.
AD7738
TIMING SPECIFICATIONS1, 2, 3
(AVDD = 5 V � 5%; DVDD = 2.7 V to 3.6 V or 5 V � 5%; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)READ OPERATION
NOTESSample tested during initial release to ensure compliance.All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.See Figures 1 and 2.These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the VOL or VOH limits.This specification is relevant only if CS goes low while SCLK is low.These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3.
The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing
characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications are subject to change without notice.
Figure 1. Read Cycle Timing Diagram
Figure 2. Write Cycle Timing Diagram
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
AD7738
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7738 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*(TA = 25�C unless otherwise noted.)
AVDD to AGND, DVDD to DGND . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . .–5 V to +5 V
AIN, AINCOM to AGND . . . . . . . . .–0.3 V to AVDD + 0.3 V
REFIN(+), REFIN(–) to AGND . . . . .–0.3 V to AVDD + 0.3 V
MUXOUT(+) to AGND . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
MUXOUT(–) to AGND . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
ADCIN(+), ADCIN(–) to AGND . . . .–0.3 V to AVDD + 0.3 V
P1 Voltage to AGND . . . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . .–0.3 V to AVDD + 0.3 V
Digital Output Voltage to DGND . . . .–0.3 V to AVDD + 0.3 V
Operating Temperature Range . . . . . . . . . . –40�C to +105�C
Storage Temperature Range . . . . . . . . . . . . –65�C to +150�C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150�C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 660 mW
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 97.9�C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .215�C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .220�C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 4. Block Diagram
ORDERING GUIDE
PIN FUNCTION DESCRIPTION9–12,
PIN CONFIGURATION
AD7738
PIN FUNCTION DESCRIPTION (continued)OUTPUT NOISE AND RESOLUTION SPECIFICATIONThe AD7738 can be operated with chopping enabled or disabled, allowing the ADC to be programmed either to optimize the
throughput rate and channel switching time or to optimize offset drift performance. Noise tables for these two primary modes of
operation are outlined below for a selection of output rates and settling times.
CHOPPING ENABLEDThe first mode, in which the AD7738 is configured with chopping enabled (CHOP = 1), provides very low noise numbers with lower
output rates. Tables I to III show the –3 dB frequencies and typical performance versus channel conversion time or equivalent output
data rate, respectively. Table I shows the typical output rms noise. Table II shows the typical effective resolution based on the rms
noise. Table III shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a
six-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise.
These typical numbers are generated from 4096 data samples acquired in Continuous Conversion mode with an analog input voltage
set to 0 V and MCLK = 6.144 MHz. The Conversion Time is selected via the Channel Conversion Time register.
Table I. Typical Output RMS Noise in �V vs. Conversion Time and Input Range with
Chopping Enabled
Table II. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with
Chopping Enabled
Table III. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with
Chopping EnabledAD7738
CHOPPING DISABLEDThe second mode, in which the AD7738 is configured with chopping disabled (CHOP = 0), provides faster conversion time while still
maintaining high resolution. Tables IV to VI show the –3 dB frequencies and typical performance versus channel conversion time or
equivalent output data rate, respectively. Table IV shows the typical output rms noise. Table V shows the typical effective resolution
based on the rms noise. Table VI shows the typical output peak-to-peak resolution, representing values for which there will be no code
flicker within a six-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise.
These typical numbers are generated from 4096 data samples acquired in Continuous Conversion mode with an analog input voltage
set to 0 V and MCLK = 6.144 MHz. The Conversion Time is selected via the Channel Conversion Time register.
Table IV. Typical Output RMS Noise in �V vs. Conversion Time and Input Range with
Chopping Disabled
Table V. Typical RMS Resolution in Bits vs. Conversion Time and Input Range with
Chopping Disabled
Table VI. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with
Chopping Disabled
TPC 1.No Missing Codes Performance, Chopping Enabled
TPC 2.No Missing Codes Performance, Chopping Disabled
TPC 3.Typical FFT Plot; Input Sinewave 183 Hz,
1.2 V Peak, Range ±1.25 V, Conversion Time
394 µs, Chopping Enabled
TPC 4.Typical Histogram; Analog Inputs Shorted;
Range ±2.5 V, Conversion Time 394 µs;
Chopping Enabled
AD7738
Table VII. Register SummaryRevision
Test
Checksum
ADC FS
Channel Data
Channel ZS Calibration
Channel FS Calibration
Channel Status
Channel Setup
Channel Conv. Time
Mode
NOTESThe three LSBs of the register address, i.e., Bit 2, Bit 1, and Bit 0 in the Communication register, specify the channel number of the register being accessed.There is only one Mode register, although the Mode register can be accessed in one of eight address locations The address used to write the Mode register specifies
the ADC channel on which the mode will be applied. Address 38h only must be used for reading from the Mode register.
Table VIII. Operational Mode SummaryTable IX. Input Range Summary
REGISTER DESCRIPTIONThe AD7738 is configurable through a series of registers. Some of them configure and control general AD7738 features, others are
specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the Communication
register, i.e., any communication to the AD7738 must start with a write to the Communication register, specifying which register
will be subsequently read or written.
Communications Register8 Bits, Write-Only Register, Address 00h
All communications to the part must start with a write operation to the Communications register. The data written to the Commu-
nications register determines whether the subsequent operation will be a read or write and to which register this operation will be
directly placed. The digital interface defaults to expect write operation to the Communication register after power on, after reset, or
after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset
by writing at least 32 serial clock cycles with DIN high and CS low (Note that all of the parts including modulator, filter, interface
and all registers are reset in this case). Remember to keep DIN low while reading 32 or more bits either in Continuous Read mode or
with the DUMP bit and “24/16” bit in the Mode register set.
Table X.
AD7738
I/O Port Register8 Bits, Read/Write Register, Address 01h, Default Value 30h + Digital Input Value � 40h
The bits in this register are used to configure and access the digital I/O pin on the AD7738.
6P1When the P1 pin is configured as an output, the P1 bit determines the pin’s output level. When the P1
Revision Register8 Bits, Read-Only Register, Address 02h, Default Value 01h + Chip Revision � 10h
Test Register24 Bits, Read/Write Register, Address 03h
This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register.
ADC Status Register8 Bits, Read-Only Register, Address 04h, Default Value 00h
In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding Channel
Data register is updated and the corresponding RDY bit is set to 1. When the Channel Data register is read, the corresponding bit is
reset to 0. The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to
the Channel Data register. Writing to the Mode register resets all the bits to 0.
In calibration modes, all the register bits are reset to 0 while a calibration is in progress and all the bits are set to 1 when the
calibration is complete.
The RDY pin output is related to the content of ADC Status register as defined by the RDY Function bit in the I/O Port register.
