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ADM1171-1AUJZ-RL7 , 2.7 V to 16.5 V Hot Swap Controller with Current Sense Output
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ADM1181AAN ,EMI/EMC Compliant, +-15 kV ESD Protected, RS-232 Line Drivers/Receiversspecifications and operate at data rates up toCMOSEIA/TIA-232OUTPUTS230 kbps.INPUTS*R2 9 8 R2R2OUT ..
AD7731BN-AD7731BR-AD7731BRU
Low Noise, High Throughput 24-Bit Sigma-Delta ADC
REV.0
Low Noise, High Throughput
24-Bit Sigma-Delta ADC
FUNCTIONAL BLOCK DIAGRAM
AIN1
AIN2
AIN3
AIN4
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
DIN
DOUT
RESETRDYPOLDGNDAGND
AVDDDVDDREF IN(–)REF IN(+)
AIN5
AIN6
GENERAL DESCRIPTIONThe AD7731 is a complete analog front-end for process control
applications. The device has a proprietary programmable gain
front end that allows it to accept a range of input signal ranges,
including low level signals, directly from a transducer. The sigma-
delta architecture of the part consists of an analog modulator
and a low pass programmable digital filter, allowing adjustment
of filter cutoff, output rate and settling time.
The part features three buffered differential programmable gain
analog inputs (which can be configured as five pseudo-differential
inputs), as well as a differential reference input. The part oper-
ates from a single +5V supply and accepts seven unipolar ana-
log input ranges: 0 to +20mV, +40mV, +80mV, +160mV,
+320mV, +640mV and +1.28 V, and seven bipolar ranges:
±20mV, ±40mV, ±80mV, ±160mV, ±320mV, ±640mV and
±1.28V. The peak-to-peak resolution achievable directly from
the part is 16 bits at an 800 Hz output rate. The part can switch
between channels with 1 ms settling time and maintain a perfor-
mance level of 13 bits of peak-to-peak resolution.
The serial interface on the part can be configured for three-wire
operation and is compatible with microcontrollers and digital
signal processors. The AD7731 contains self-calibration and
system calibration options and features an offset drift of less
than 5nV/°C and a gain drift of less than 2ppm/°C.
The part is available in a 24-lead plastic DIP, a 24-lead SOIC
and 24-lead TSSOP package.
FEATURES
24-Bit Sigma-Delta ADC
16 Bits p-p Resolution at 800 Hz Output Rate
Programmable Output Rates up to 6.4 kHz
Programmable Gain Front End60.0015% Nonlinearity
Buffered Differential Inputs
Programmable Filter Cutoffs
FASTStep™* Mode for Channel Sequencing
Single Supply Operation
APPLICATIONS
Process Control
PLCs/DCS
Industrial Instrumentation
*FASTStep is a trademark of Analog Devices, Inc.
AD7731–SPECIFICATIONSSTATIC PERFORMANCE (CHP = 0)
STATIC PERFORMANCE (CHP = 1)
ANALOG INPUTS/REFERENCE INPUTS
(AVDD = +5V, DVDD = +3V or +5V; REF IN(+) = +2.5V; REFIN(–) = AGND; AGND =
DGND = 0V; fCLK IN = 4.9152MHz. All specifications TMIN to TMAX unless otherwise noted.)
AD7731LOGIC OUTPUTS (Including MCLK OUT)
TRANSDUCER BURNOUT
SYSTEM CALIBRATION
POWER REQUIREMENTS
AD7731NOTESTemperature Range: –40°C to +85°C.Sample tested during initial release.No missing codes performance with CHP = 0 and SKIP = 1 is 22 bits.The offset (or zero) numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2μV typical. Offset numbers with CHP = 1 are typicallyμV precalibration. Internal zero-scale calibration reduces this by about 1 μV. System zero-scale calibration reduces offset numbers with CHP = 0 and CHP = 1 to the order of the
noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on all input ranges except the 20mV and 40mV input
range reduces the gain error to less than 100 ppm. When operating on the 20mV or 40mV range, an internal full-scale calibration should be performed on the 80mV input range with
a resulting gain error of less than 250ppm. System full-scale calibration reduces the gain error on all input ranges to the order of the noise. Positive and Negative Full-Scale Errors can
be calculated from the offset and gain errors.These numbers are generated during life testing of the part.Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology.Recalibration at any temperature will remove these errors.Full-scale drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points use to calculate the gain error are
positive full-scale and negative full-scale. See Terminology.Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed.Power Supply Rejection and Common-Mode Rejection are given here for the upper and lower input voltage ranges. The rejection can be approximated to varying linearly (in dBs)
between these values for the other input ranges.The analog input voltage range on the AIN(+) inputs is given here with respect to the voltage on the respective AIN(–) input.The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed.These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.VDD refers to DVDD for all logic outputs expect D0 and D1 where it refers to AVDD. In other words, the output logic high for these two outputs is determined by AVDD.See Burnout Current section.After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar
zero point.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2NOTES
1Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2See Figures 15 and 16.
3SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.
5This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is required primarily for interfacing to
(AVDD = +4.75V to +5.25V; DVDD = +2.7V to +5.25 V; AGND = DGND = 0 V;
fCLK IN = 4.9152 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –5V to +0.3V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –2V to +5V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3V
Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3V
AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . . 30 mA
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Output Voltage (D0, D1) to DGND . .–0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDEAD7731BR
AD7731BRU
TO OUTPUT
PIN
50pF
ISINK (800µA AT DVDD = +5V 100µA AT DVDD = +3V)
+1.6V
ISOURCE (200µA AT DVDD = +5V
100µA AT DVDD = +3V)Figure 1.Load Circuit for Access Time and Bus Relinquish Time
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7731 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD7731
AIN3/D1
AIN4/D0
*SPI IS A TRADEMARK OF MOTOROLA, INC.Figure 2.Detailed Functional Block Diagram
Figure 3.Signal Processing Chain
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
AD7731
PIN FUNCTION DESCRIPTIONS (Continued)PIN FUNCTION DESCRIPTIONS (Continued)
TERMINOLOGY
INTEGRAL NONLINEARITYThis is the maximum deviation of any code from a straight line
passingthroughtheendpointsofthetransferfunction. The end-
points of the transfer function are zero scale (not to be confused
withbipolarzero),apoint0.5 LSBbelowthefirstcode transi-
tion (000...000 to 000...001) and full scale, a point 0.5LSB
abovethelastcodetransition(111...110to 111...111). The
error is expressed as a percentage of full scale.
POSITIVE FULL-SCALE ERRORPositive Full-Scale Error is the deviation of the last code transi-
tion (111...110 to 111...111) from the ideal AIN(+) voltage
(AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar
and bipolar analog input ranges.
UNIPOLAR OFFSET ERRORUnipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
BIPOLAR ZERO ERRORThis is the deviation of the midscale transition (0111...111
to 1000...000) fromtheidealAIN(+)voltage(AIN(–)–
0.5LSB) when operating in the bipolar mode.
GAIN ERRORThis is a measure of the span error of the ADC. It is a measure
of the difference between the measured and the ideal span be-
tween any two points in the transfer function. The two points
used to calculate the gain error are positive full scale and nega-
tive full scale.
BIPOLAR NEGATIVE FULL-SCALE ERRORThis is the deviation of the first code transition from the ideal
POSITIVE FULL-SCALE OVERRANGEPositive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages on AIN(+) input greater than
AIN(–) + VREF/GAIN (for example, noise peaks or excess volt-
ages due to system gain errors in system calibration routines)
without introducing errors due to overloading the analog modu-
lator or overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGEThis is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – VREF/GAIN without overloading the
analog modulator or overflowing the digital filter.
OFFSET CALIBRATION RANGEIn the system calibration modes, the AD7731 calibrates its
offset with respect to the analog input. The Offset Calibration
Range specification defines the range of voltages the AD7731
can accept and still accurately calibrate offset.
FULL-SCALE CALIBRATION RANGEThis is the range of voltages that the AD7731 can accept in the
system calibration mode and still accurately calibrate full scale.
INPUT SPANIn system calibration schemes, two voltages applied in sequence
to the AD7731’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full scale that the AD7731 can
accept and still accurately calibrate gain.
AD7731
OUTPUT NOISE AND RESOLUTION SPECIFICATIONThe AD7731 has a number of different modes of operation of the on-chip filter and chopping features. These options are discussed
in more detail in later sections. The part can be programmed either to optimize the throughput rate and settling time or to optimize
noise and drift performance. Noise tables for two of the primary modes of operation of the part are outlined below for a selection of
output rates and settling times. The first mode, where the AD7731 is configured with CHP = 0 and SKIP mode enabled, provides
fast settling time while still maintaining high resolution. The second mode, where CHP = 1 and the full second filter is included,
provides very low noise numbers with lower output rates. Settling time refers to the time taken to get an output that is 100% settled
to the new value after a channel change or exercising SYNC.
Output Noise (CHP = 0, SKIP = 1)Table I shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in
nonchop mode (CHP of Filter Register = 0) and with the second filter bypassed (SKIP of Filter Register = 1). The table is generated
with a master clock frequency of 4.9152 MHz. These numbers are typical and generated at a differential analog input voltage of 0V.
The output update rate is selected via the SF0 to SF11 bits of the Filter Register. Table II, meanwhile, shows the output peak-to-
peak resolution in bits (rounded to the nearest 0.5LSB) for the same output update rates. It is important to note that the numbers in
Table II represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on
rms noise but on peak-to-peak noise.
The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in Table I will remain the same for unipolar ranges. To calculate
the numbers for Table II for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits.
Table I.Output Noise vs. Input Range and Update Rate (CHP = 0, SKIP = 1)
Typical Output RMS Noise in mV
Table II.Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0, SKIP = 1)
Peak-to-Peak Resolution in Bits
Output Noise (CHP = 1, SKIP = 0)Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in
chopping mode (CHP of Filter Register = 1) and with the second filter included in the loop. The numbers are generated with a mas-
ter clock frequency of 4.9152 MHz. These numbers are typical and generated at a differential analog input voltage of 0 V. The out-
put update rate is selected via the SF0 to SF11 bits of the Filter Register. Table IV, meanwhile, shows the output peak-to-peak
resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in
Table IV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on
rms noise but on peak-to-peak noise.
The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in Table III will remain the same for unipolar ranges. To calcu-
late the number for Table IV for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits.
Table III.Output Noise vs. Input Range and Update Rate (CHP = 1, SKIP = 0)
Typical Output RMS Noise in nV
Table IV.Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1, SKIP = 0)
Peak-to-Peak Resolution in Bits
ON-CHIP REGISTERSThe AD7731 contains 12 on-chip registers that can be accessed
via the serial port of the part. These registers are summarized in
Figure 4 and in Table V, and described in detail in the following
sections.
AD7731
Table V.Summary of On-Chip Registers
Power-On/Reset
Register NameTypeSizeDefault ValueFunctionCommunicationsWrite Only8 BitsNot ApplicableAll operations to other registers are initiated through
Registerthe Communications Register. This controls whether
subsequent operations are read or write operations
and also selects the register for that subsequent opera-
tion. Most subsequent operations return control to
the Communications Register except for the continu-
ous read mode of operation.
Status RegisterRead Only8 BitsCX HexProvides status information on conversions, calibra-
tions, settling to step inputs, standby operation and
the validity of the reference voltage.
Data RegisterRead Only16 Bits or 24 Bits000000 HexProvides the most up-to-date conversion result from
the part. Register length can be programmed to be
16 bit or 24 bit.
Mode RegisterRead/Write16 Bits0174 HexControls functions such as mode of operation, uni-
polar/bipolar operation, controlling the function of
AIN3/D1 and AIN4/D0, burnout current and Data
Register word length. It also contains the reference
selection bit, the range selection bits and the channel
selection bits.
Filter RegisterRead/Write16 Bits2002 HexControls the amount of averaging in the first stage
filter, selects the fast step and skip modes and con-
trols the chopping modes on the part.
Offset RegisterRead/Write24 BitsContains a 24-bit word which is the offset calibration
coefficient for the part. The contents of this register
are used to provide offset correction on the output
from the digital filter. There are three Offset Regis-
ters on the part and these are associated with input
channel pairs as outlined in Table XIII.
Gain RegisterRead/Write24 BitsContains a 24-bit word which is the gain calibration
coefficient for the part. The contents of this register
are used to provide gain correction on the output
from the digital filter. There are three Gain Registers
on the part and these are associated with input chan-
nel pairs as outlined in Table XIII.
Test RegisterRead/Write24 Bits000000 HexControls the test modes of the part which are used
when testing the part. The user is advised not to
change the contents of this register.
Communications Register (RS2-RS0 = 0, 0, 0)The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the
Communications Register. The data written to the Communications Register determines whether the next operation is a read or
write operation, the type of read operation and to which register this operation takes place. For single-shot read or write operations,
once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write op-
eration to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7731 is
in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a
write operation of at least 32 serial clock cycles with DIN high, returns the AD7731 to this default state by resetting the part. Table
VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits
are in the Communications Register. CR7 denotes the first bit of the data stream.
Table VI.Communications RegisterRC6RC5RC4RC3RC2RC1RC0RC
BitBit
LocationMnemonicDescriptionCR7WENWrite Enable Bit. A 0 must be written to this bit so the write operation to the Communica-
tions Register actually takes place. If a 1 is written to this bit, the part will not clock on to
subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit.
Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communica-
tions Register.
CR6ZEROA zero must be written to this bit to ensure correct operation of the AD7731.
CR5, CR4RW1, RW0Read Write Mode Bits. These two bits determine the nature of the subsequent read/write
operation. Table VII outlines the four options.
Table VII.Read/Write ModeWith 0, 0 written to these two bits, the next operation is a write operation to the register
specified by bits RS2, RS1, RS0. Once the subsequent write operation to the specified regis-
ter has been completed, the part returns to where it is expecting a write operation to the
Communications Register.
With 0, 1 written to these two bits, the next operation is a read operation of the register specified
by bits RS2, RS1, RS0. Once the subsequent read operation to the specified register has been
completed, the part returns to where it is expecting a write operation to the Communications
Register.
Writing 1, 0 to these bits, sets the part into a mode of continuous reads from the register
specified by bits RS2, RS1, RS0. The most likely registers which the user will want to use this
function with are the Data Register and the Status Register. Subsequent operations to the
part will consist of read operations to the specified register without any intermediate writes to
the Communications Register. This means that once the next read operation to the specified
register has taken place, the part will be in a mode where it is expecting another read from
that specified register. The part will remain in this continuous read mode until 30 Hex has
been written to bits RW1 and RW0.
When 1, 1 is written to these bits (and 0 written to bits CR3 through CR0), the continuous
read mode is stopped and the part returns to where it is expecting a write operation to the
Communications Register. Note, the part continues to look at the DIN line on each SCLK
edge during the continuous read mode so that it can determine when to stop the continuous
AD7731
BitBit
LocationMnemonicDescriptionCR3ZEROA zero must be written to this bit to ensure correct operation of the AD7731.
CR2-CR0RS2-RS0Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select to which
one of eight on-chip registers the next read or write operation takes place as shown in Table VIII.
Table VIII.Register Selection
Status Register (RS2-RS0 = 0, 0, 0); Power-On/Reset Status: CX HexThe Status Register is an 8-bit read-only register. To access the Status Register, the user must write to the Communications Register
selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig-
nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 de-
notes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7731. The number in brackets
indicates the power-on/reset default status of that bit.
Table IX.Status RegisterRS6RS5RS4RS3RS2RS1RS0RS
BitBit
LocationMnemonicDescriptionSR7RDYReady Bit. This bit provides the status of the RDY flag from the part. The status and func-
tion of this bit is the same as the RDY output pin. A number of events set the RDY bit high
as indicated in Table XVII.
SR6STDYSteady Bit. This bit is updated when the filter writes a result to the Data Register. If the filter
is in FASTStep™ mode (see Filter Register section), and responding to a step input, the
STDY bit remains high as the initial conversion results become available. The RDY output
and bit are set low on these initial conversions to indicate that a result is available. However,
if the STDY is high, it indicates that the result being provided is not from a fully settled
second-stage FIR filter. When the FIR filter has fully settled, the STDY bit will go low coin-
cident with RDY. If the part is never placed into its FASTStep™ mode, the STDY bit will go
low at the first Data Register read and it is not cleared by subsequent Data Register reads.
A number of events set the STDY bit high as indicated in Table XVII. STDY is set high
along with RDY by all events in the table except a Data Register read.
SR5STBYStandby Bit. This bit indicates whether the AD7731 is in its Standby Mode or normal mode
of operation. The part can be placed in its standby mode using the STANDBY input pin or
by writing 011 to the MD2 to MD0 bits of the Mode Register. The power-on/reset status of
this bit is 0 assuming the STANDBY pin is high.
SR4NOREFNo Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.5 V
or either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on
completion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on
Data Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 000000 HexThe Data Register on the part is a read-only register that contains the most up-to-date conversion result from the AD7731. Figure 5
shows a flowchart for reading from the registers on the AD7731. The register can be programmed to be either 16 or 24 bits wide,
determined by the status of the WL bit of the Mode Register. The RDY output and RDY bit of the Status Register are set low when
the Data Register is updated. The RDY pin and RDY bit will return high once the full contents of the register (either 16 or 24 bits)
have been read. If the Data Register has not been read by the time the next output update occurs, the RDY pin and RDY bit will go
high for at least 158.5 × tCLK IN indicating when a read from the Data Register should not be initiated to avoid a transfer from the
Data Register as it is being updated. Once the updating of the Data Register has taken place, RDY returns low.
If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place
in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the inter-
face). However, the 16 or 24 bits of data written to the part will be ignored by the AD7731.
Mode Register (RS2-RS0 = 0, 1, 0); Power-On/Reset Status: 0174HexThe Mode Register is a 16-bit register from which data can either be read or to which data can be written. This register configures
the operating modes of the AD7731, the input range selection, the channel selection and the word length of the Data Register. TableX
outlines the bit designations for the Mode Register. MR0 through MR15 indicate the bit location, MR denoting the bits are in the
Mode Register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of
that bit. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the
registers on the part.
Table X.Mode Register1RM41RM31RM21RM11RM01RM9RM8RMRM6RM5RM4RM3RM2RM1RM0RM
BitBit
LocationMnemonicDescriptionMR15–MR13MD2–MD0Mode Bits. These three bits determine the mode of operation of the AD7731 as outlined in
Table XI. The modes are independent, such that writing new mode bits to the Mode Regis-
ter will exit the part from the mode in which it is operating and place it in the new requested
mode immediately after the Mode Register write. The function of the mode bits is described
in more detail below.
Table XI.Operating Modes
AD7731
MD2MD1MD0Operating Mode00Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7731 is not
processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC
input pin. However, exerting the SYNC does not actually force these mode bits to 0, 0, 0. The part re-
turns to this mode after a calibration or after a conversion in Single Conversion Mode. This is the default
condition of these bits after Power-On/Reset.01Continuous Conversion Mode. In this mode, the AD7731 is continuously processing data and providing
conversion results to the Data Register at the programmed output update rate (as determined by the
Filter Register). For most applications, this would be the normal operating mode of the AD7731.10Single Conversion Mode. In this mode, the AD7731 performs a single conversion, updates the Data
Register, returns to the Sync Mode and resets the mode bits to 0, 0, 0. The result of the single conversion
on the AD7731 in this mode will not be provided until the full settling-time of the filter has elapsed.11Power-Down (Standby) Mode. In this mode, the AD7731 goes into its power-down or standby state. Placing
the part in this mode is equivalent to exerting the STANDBY input pin. However, exerting STANDBY does
not actually force these mode bits to 0, 1, 1.00Zero-Scale Self-Calibration Mode. This activates zero-scale self-calibration on the channel selected by the
CH2, CH1 and CH0 bits of the Mode Register. This zero-scale self-calibration is performed at the se-
lected gain on internally shorted (zeroed) inputs. When this zero-scale self-calibration is complete, the
part updates the contents of the Offset Calibration Register and returns to Sync Mode with MD2, MD1
and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return
low when this zero-scale self-calibration is complete to indicate that the part is back in Sync Mode and
ready for further operations.01Full-Scale Self-Calibration Mode. This activates full-scale self-calibration on the channel selected by the
CH2, CH1 and CH0 bits of the Mode Register. This full-scale self-calibration is performed at the se-
lected gain on an internally-generated full-scale signal. When this full-scale self-calibration is complete,
the part updates the contents of the Gain Calibration Register and returns to Sync Mode with MD2,
MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and
return low when this full-scale self-calibration is complete to indicate that the part is back in Sync Mode
and ready for further operations.10Zero-Scale System Calibration Mode. This activates zero scale system calibration on the channel selected
by the CH2, CH1 and CH0 bits of the Mode Register. Calibration is performed at the selected gain on
the input voltage provided at the analog input during this calibration sequence. This input voltage should
remain stable for the duration of the calibration. When this zero-scale system calibration is complete, the
part updates the contents of the Offset Calibration Register and returns to Sync Mode with MD2, MD1
and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return
low when this zero-scale calibration is complete to indicate that the part is back in Sync Mode and ready
for further operations.11Full-Scale System Calibration Mode. This activates full-scale system calibration on the selected input
channel. Calibration is performed at the selected gain on the input voltage provided at the analog input
during this calibration sequence. This input voltage should remain stable for the duration of the calibra-
tion. When this full-scale system calibration is complete, the part updates the contents of the Gain Cali-
bration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY
output and bit go high when calibration is initiated and return low when this full-scale calibration is com-
plete to indicate that the part is back in Sync Mode and ready for further operations.
BitBit
LocationMnemonicDescriptionMR12B/UBipolar/Unipolar Bit. A 0 in this bit selects bipolar operation and the output coding is
00...000 for negative full-scale input, 10...000 for zero input and 11...111 for positive full-
scale input. A 1 in this bit selects unipolar operation and the output coding is 00...000 for
zero input and 11...111 for positive full-scale input.
MR11DENDigital Output Enable Bit. With this bit at 1, the AIN3/D1 and AIN4/D0 pins assume their
digital output functions and the output drivers connected to these pins are enabled. In this
mode, the user effectively has two port bits which can be programmed over the serial interface.
MR10–MR9D1–D0Digital Output Bits. These bits determine the digital outputs on the AIN3/D1 and AIN4/D0
pins respectively when the DEN bit is a 1. For example, a 1 written to the D1 bit of the
Mode Register (with the DEN bit also a 1) will put a logic 1 on the AIN3/D1 pin. This logic
1 will remain on this pin until a 0 is written to the D1 bit (in which case, the AIN3/D1 pin
goes to a logic 0) or the digital output function is disabled by writing a 0 to the DEN bit.
MR8WLData Word Length Bit. This bit determines the word length of the Data Register. A 0 in this
bit selects 16-bit word length when reading from the data register (i.e., RDY returns high
after 16 serial clock cycles in the read operation). A 1 in this bit selects 24-bit word length for
the Data Register.
MR7HIREFHigh Reference Bit. This bit should be set in accordance with the reference voltage which is
being used on the part. If the reference voltage is 2.5 V, the HIREF bit should be set to 0. If
the reference voltage is 5 V, the HIREF bit should be set to a 1. With the HIREF bit set
correctly for the appropriate applied reference voltage, the input ranges are 0mV to +20mV,
+40mV, +80mV, +160 mV, +320 mV, +640 mV and +1.28 V for unipolar operation and
±20mV, ±40mV, ±80mV, ±160 mV, ±320 mV, ±640 mV and ±1.28 V for bipolar operation.
It is possible for a user with a 2.5 V reference to set the HIREF bit to a 1. In this case, the
part is operating with a 2.5 V reference but assumes it has a 5 V reference. As a result, the
input ranges on the part become 0mV to +10mV through 0mV to +640 mV for unipolar
operation and ±10mV through ±640 mV for bipolar operation. However, the output noise
from the part (in nV) will remain unchanged so the resolution of the part (in LSBs) will re-
duce by 1.
MR6–MR4RN2–RN0Input Range Bits. These bits determine the analog input range for the selected analog input.
The different input ranges are outlined in Table XII. The table is valid for a reference voltage
of 2.5 V with the HIREF bit at 0 or for a reference voltage of 5 V with the HIREF bit at a
logic 1.
Table XII.Input Range Selection
AD7731
BitBit
LocationMnemonicDescriptionMR3BOBurnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout
currents connect to the selected analog input pair, one source current to the AIN(+) input
and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout
currents.
MR2–MR0CH2–CH0Channel Select. These three bits select a channel either for conversion or for access to cali-
bration coefficients as outlined in Table XIII. There are three pairs of calibration registers on
the part. In fully differential mode, the part has three input channels so each channel has its
own pair of calibration registers. In pseudo-differential mode, the AD7731 has five input
channels with some of the input channel combinations sharing calibration registers. With
CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself.
This can be used as a test method to evaluate the noise performance of the part with no ex-
ternal noise sources. In this mode, the AIN6 input should be connected to an external volt-
age within the allowable common-mode range for the part. The power-on/default status of
these bits is 1, 0, 0.
Table XIII.Channel Selection
Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002HexThe Filter Register is a 16-bit register from which data can either be read or to which data can be written. This register determines
the amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode. Table XIV
outlines the bit designations for the Filter Register. FR0 through FR15 indicate the bit location, FR denoting the bits are in the Filter
Register. FR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers
on the part.
Table XIV.Filter Register1RF41RF31RF21RF11RF01RF9RF8RFRF6RF5RF4RF3RF2RF1RF0RF
BitBit
LocationMnemonicDescriptionFR15–FR4SF11–SF0Sinc3 Filter Selection Bits. The AD7731 contains two filters, a Sinc3 filter and an FIR filter.
The 12 bits programmed to SF11 through SF0 sets the amount of averaging which the Sinc3
filter performs. As a result, the number programmed to these 12 bits affects the –3 dB fre-
quency and output update rate from the part (see Filter Architecture section). The allowable
Table XV.SF Ranges
BitBit
LocationMnemonicDescriptionFR3ZEROA zero must be written to this bit to ensure correct operation of the AD7731.
FR2CHPChop Enable Bit. This bit determines if the chopping mode on the part is enabled. A 1 in this
bit location enables chopping on the part. When the chop mode is enabled, the part is effec-
tively chopped at its input and output to remove all offset and offset drift errors on the part.
If offset performance with time and temperature are important parameters in the design, it is
recommended that the user enable chopping on the part.
FR1SKIPFIR Filter Skip Bit. With a 0 in this bit, the AD7731 performs two stages of filtering before
shipping a result out of the filter. The first is a Sinc3 filter followed by a 22-tap FIR filter.
With a 1 in this bit, the FIR filter on the part is bypassed and the output of the Sinc3 is fed
directly as the output result of the AD7731’s filter (see Filter Architecture for more details on
the filter implementation).
FR0FASTFASTStep™ Mode Enable Bit. A 1 in this bit enables the FASTStep™ mode on the AD7731. In
this mode, if a step change on the input is detected, the FIR calculation portion of the filter is
suspended and replaced by a simple moving average on the output of the Sinc3 filter. Ini-
tially, two outputs from the sinc3 filter are used to calculate an AD7731 output. The number
of sinc3 outputs used to calculate the moving average output is increased (from 2 to 4 to 8 to
16) until the STDY bit goes low. When the FIR filter has fully settled after a step, the STDY
bit will become active and the FIR filter is switched back into the processing loop (see Filter
Architecture section for more details on the FASTStep™ mode).
Offset Calibration Register (RS2–RS0 = 1, 0, 1)The AD7731 contains three 24-bit Offset Calibration Registers, labeled Offset Calibration Register 0 to Offset Calibration Register
2, to which data can be written and from which data can be read. The three registers are totally independent of each other such that
in fully-differential mode there is an offset register for each of the input channels. This register is used in conjunction with the associ-
ated Gain Calibration Register to form a register pair. The calibration register pair used to scale the output of the filter is as outlined
in Table XIII. To access the appropriate Offset Calibration Register the user should write first to the Mode Register setting up the
appropriate address in the CH2 to CH0 bits.
The Offset Calibration Register is updated after an offset calibration routine (1, 0, 0 or 1, 1, 0 loaded to the MD2, MD1, MD0 bits
of the Mode Register). During subsequent conversions, the contents of this register are subtracted from the filter output prior to gain
scaling being performed on the word. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a
flowchart for writing to the registers on the part.
Gain Calibration Register (RS2–RS0 = 1, 1, 0)The AD7731 contains three 24-bit Gain Calibration Registers to which data can be written and from which data can be read. The
three registers are totally independent of each other such that in fully-differential mode there is a gain register for each of the input
channels. This register is used in conjunction with the associated Offset Calibration Register to form a register pair which scale the
output of the filter before it is loaded to the Data Register. These register pairs are associated with input channel pairs as outlined in
Table XIII. To access the appropriate Gain Calibration Register the user should write first to the Mode Register setting up the ap-
propriate address in the CH2 to CH0 bits.
The Gain Calibration Register is updated after a gain calibration routine (1, 0, 1 or 1, 1, 1 loaded to the MD2, MD1, MD0 bits of
the Mode Register). During subsequent conversions, the contents of this register are used to scale the number which has already
been offset corrected with the Offset Calibration Register contents. Figure 5 shows a flowchart for reading from the registers on the
AD7731 and Figure 6 shows a flowchart for writing to the registers on the part.
Test Register (RS2–RS0 = 1, 1, 1); Power On/Reset Status: 000000HexThe AD7731 contains a 24-bit Test Register to which data can be written and from which data can be read. The contents of this
register are used in testing the device. The user is advised not to change the status of any of the bits in this register from the default
AD7731
READING FROM AND WRITING TO THE ON-CHIP REGISTERSThe AD7731 contains a total of twelve on-chip registers. These registers are all accessed over a three-wire interface. As a result,
addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a
flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of
the registers. Figure 6 gives a flowchart for writing to the different registers on the part, again summarizing the sequence and words
to be written to the AD7731.
*N/A = Not Applicable. Continuous reads of these registers does
not make sense as the register contents would remain the same
since they are only changed by a write operation.
Figure 5.Flowchart for Reading from the AD7731 Registers
START
CALIBRATION OPERATION SUMMARYThe AD7731 contains a number of calibration options as outlined previously. Table XVI summarizes the calibration types, the op-
erations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to
monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method is to do a software poll of the
RDY bit in the Status Register. This can be achieved by setting up the part for continuous reads of the Status Register once a calibra-
tion has been initiated. The RDY pin and RDY bit go high on initiating a calibration and return low at the end of the calibration
routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. The FAST and SKIP bits are treated
as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full details.
Table XVI.Calibration OperationsInternal Full-Scale
System Zero-Scale
System Full-Scale
AD7731
CIRCUIT DESCRIPTIONThe AD7731 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low-frequency signals such as those in strain-gage, pressure
transducer, temperature measurement, industrial control or pro-
cess control applications. It contains a sigma-delta (or charge-
balancing) ADC, a calibration microcontroller with on-chip
static RAM, a clock oscillator, a digital filter and a bidirectional
serial communications port. The part consumes 13.5mA of
power supply current with a standby mode which consumes
only 20μA. The part operates from a single +5 V supply. The
clock source for the part can be provided via an external clock
or by connecting a crystal oscillator or ceramic resonator across
the MCLKIN or MCLKOUT pins.
The part contains three programmable-gain fully differential
analog input channels which can be reconfigured as five pseudo-
differential inputs. The part handles a total of seven different
input ranges on all channels which are programmed via the on-
chip registers. The differential unipolar ranges are: 0mV to
+20mV through 0 V to +1.28 V and the differential bipolar
ranges are: ±20mV through ±1.28 V.
The AD7731 employs a sigma-delta conversion technique to
realize up to 24 bits of no missing codes performance. The
sigma-delta modulator converts the sampled input signal into a
digital pulse train whose duty cycle contains the digital informa-
tion. A digital low-pass filter processes the output of the sigma-
delta modulator and updates the data register at a rate that can
be programmed over the serial interface. The output data from
the part is accessed over this serial interface. The cutoff fre-
quency and output rate of this filter can be programmed via on-
chip registers. The output noise performance and peak-to-peak
resolution of the part varies with gain and with the output rate
as shown in Tables I to IV.
The analog inputs are buffered on-chip, allowing the part to
handle significant source impedances on the analog input. This
means that external R, C filtering (for noise rejection or RFI
interference reduction) can be placed on the analog inputs if
required. The common-mode voltage range for the analog in-
puts comes within 1.2V of AGND and 0.95V of AVDD. The
reference input is also differential and the common-mode range
here is from AGND to AVDD.
The AD7731 contains a number of hardware and software
events that set or reset status flags and bits in registers. Table
XVII summarizes which blocks and flags are affected by the
different events.
Table XVII.Reset Events
