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AD7730BN-AD7730BRU
Bridge Transducer ADC
REV.A
Bridge Transducer ADC
FUNCTIONAL BLOCK DIAGRAM
KEY FEATURES
Resolution of 230,000 Counts (Peak-to-Peak)
Offset Drift: 5 nV/8C
Gain Drift: 2ppm/8C
Line Frequency Rejection: >150dB
Buffered Differential Inputs
Programmable Filter Cutoffs
Specified for Drift Over Time
Operates with Reference Voltages of 1V to 5V
ADDITIONAL FEATURES
Two-Channel Programmable Gain Front End
On-Chip DAC for Offset/TARE Removal
FASTStep™ Mode
AC or DC Excitation
Single Supply Operation
APPLICATIONS
Weigh Scales
Pressure Measurement
GENERAL DESCRIPTION
The AD7730 is a complete analog front end for weigh-scale and
pressure measurement applications. The device accepts low-
level signals directly from a transducer and outputs a serial
digital word. The input signal is applied to a proprietary pro-
grammable gain front end based around an analog modulator.
FASTStep is a trademark of Analog Devices, Inc.
VBIAS
AIN1(+)
AIN1(–)
AIN2(+)/D1
AIN2(–)/D0
ACX
ACX
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
DIN
DOUT
RESETRDYPOLDGNDAGND
AVDDDVDDREF IN(–)REF IN(+)
The modulator output is processed by a low pass programmable
digital filter, allowing adjustment of filter cutoff, output rate and
settling time.
The part features two buffered differential programmable gain
analog inputs as well as a differential reference input. The part
operates from a single +5V supply. It accepts four unipolar
analog input ranges: 0 mV to +10mV, +20mV, +40mV and
+80mV and four bipolar ranges: ±10mV, ±20mV, ±40mV
and ±80mV. The peak-to-peak resolution achievable directly
from the part is 1 in 230,000 counts. An on-chip 6-bit DAC
allows the removal of TARE voltages. Clock signals for synchro-
nizing ac excitation of the bridge are also provided.
The serial interface on the part can be configured for three-wire
operation and is compatible with microcontrollers and digital
signal processors. The AD7730 contains self-calibration and
system calibration options, and features an offset drift of less
than 5 nV/°C and a gain drift of less than 2 ppm/°C.
The AD7730 is available in a 24-pin plastic DIP, a 24-lead
SOIC and 24-lead TSSOP package. The AD7730L is available
in a 24-lead SOIC and 24-lead TSSOP package.
NOTE
The description of the functions and operation given in this data
sheet apply to both the AD7730 and AD7730L. Specifications
and performance parameters differ for the parts. Specifications
for the AD7730L are outlined in Appendix A.
AD7730–SPECIFICATIONS
(AVDD = +5V, DVDD = +3V or +5V; REF IN(+) = AVDD; REFIN(–) = AGND = DGND =V; fCLK IN = 4.9152 MHz. All specifications TMIN to TMAX unless otherwise noted.)
AD7730/AD7730L
AD7730/AD7730L
NOTESTemperature range: –40°C to +85°C.Sample tested during initial release.The offset (or zero) numbers with CHP = 1 are typically 3μV precalibration. Internal zero-scale calibration reduces this by about 1μV. Offset numbers with CHP = 0 can be up tomV precalibration. Internal zero-scale calibration reduces this to 2μV typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the
noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on the 80 mV range reduces the gain error to less than
100ppm for the 80 mV and 40 mV ranges, to about 250 ppm for the 20 mV range and to about 500 ppm on the 10 mV range. System full-scale calibration reduces this to the order of
the noise. Positive and negative full-scale errors can be calculated from the offset and gain errors.These numbers are generated during life testing of the part.Positive Full-Scale Error includes Offset Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology.Recalibration at any temperature will remove these errors.Full-Scale Drift includes Offset Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points used to calculate the gain
error are positive full scale and negative full scale. See Terminology.Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed.No Missing Codes performance with CHP = 0 and SKIP = 1 is reduced below 24 bits for SF words lower than 180 decimal.The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs respectively.The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed.These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.VDD refers to DVDD for all logic outputs expect D0, D1, ACX and ACX where it refers to AVDD. In other words, the output logic high for these four outputs is determined by AVDD.This number represents the total drift of the channel with a zero input and the DAC output near full scale.After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, the device outputs all 0s.These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the
bipolar zero point.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2
NOTESSample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.See Figures 18 and 19.SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is primarily required for
interfacing to DSP machines.
(AVDD = +4.75V to +5.25V; DVDD = +2.7V to +5.25 V; AGND = DGND = 0 V; fCLK IN = 4.9152MHz;
Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7730 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . .–0.3V to +7V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –5V to +0.3V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . –2V to +5V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3V
Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3V
AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . 30 mA
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Output Voltage (ACX, ACX, D0, D1) to DGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
ORDERING GUIDE
Plastic DIP Package, Power Dissipation . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . +260°C
TSSOP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . 128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in
the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
TO OUTPUT
PIN
+1.6V
Figure 1.Load Circuit for Access Time and Bus Relinquish Time
AD7730/AD7730L
Figure 2.Detailed Functional Block Diagram
Figure 3.Signal Processing Chain
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
AD7730/AD7730L
TERMINOLOGY
INTEGRAL NONLINEARITY
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.
POSITIVE FULL-SCALE ERROR
Positive Full-Scale Error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage
(AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar
and bipolar analog input ranges. Positive full-scale error is a
summation of offset error and gain error.
UNIPOLAR OFFSET ERROR
Unipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
BIPOLAR ZERO ERROR
This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB)
when operating in the bipolar mode.
GAIN ERROR
This is a measure of the span error of the ADC. It is a measure
of the difference between the measured and the ideal span be-
tween any two points in the transfer function. The two points
BIPOLAR NEGATIVE FULL-SCALE ERROR
This is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB) when operat-
ing in the bipolar mode. Negative full-scale error is a summation
of zero error and gain error.
POSITIVE FULL-SCALE OVERRANGE
Positive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages on AIN(+) input greater than
AIN(–) + VREF/GAIN (for example, noise peaks or excess volt-
ages due to system gain errors in system calibration routines) with-
out introducing errors due to overloading the analog modulator
or overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGE
This is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – VREF/GAIN without overloading the
analog modulator or overflowing the digital filter.
OFFSET CALIBRATION RANGE
In the system calibration modes, the AD7730 calibrates its
offset with respect to the analog input. The Offset Calibration
Range specification defines the range of voltages the AD7730
can accept and still accurately calibrate offset.
FULL-SCALE CALIBRATION RANGE
This is the range of voltages that the AD7730 can accept in the
system calibration mode and still calibrate full scale correctly.
INPUT SPAN
AD7730/AD7730L
OUTPUT NOISE AND RESOLUTION SPECIFICATION
The AD7730 can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or
dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. These
options are discussed in more detail in later sections. The chop mode has the advantage of lower drift numbers and better noise im-
munity, but the noise is approximately 20% higher for a given –3 dB frequency and output data rate. It is envisaged that the majority
of weigh-scale users of the AD7730 will operate the part in chop mode to avail themselves of the excellent drift performance and
noise immunity when chopping is enabled. The following tables outline the noise performance of the part in both chop and nonchop
modes over all input ranges for a selection of output rates. Settling time refers to the time taken to get an output that is 100% settled
to new value.
Output Noise (CHP = 1)
This mode is the primary mode of operation of the device. Table I shows the output rms noise for some typical output update rates
and –3 dB frequencies for the AD7730 when used in chopping mode (CHP of Filter Register = 1) with a master clock frequency of
4.9152 MHz. These numbers are typical and are generated at a differential analog input voltage of 0 V. The output update rate is
selected via the SF0 to SF11 bits of the Filter Register. Table II, meanwhile, shows the output peak-to-peak resolution in counts for
the same output update rates. The numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5
LSB). It is important to note that the numbers in Table II represent the resolution for which there will be no code flicker within a
six-sigma limit. They are not calculated based on rms noise, but on peak-to-peak noise.
The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in Table I will remain the same for unipolar ranges while the
numbers in Table II will change. To calculate the numbers for Table II for unipolar input ranges simply divide the peak-to-peak
resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.
Table I.Output Noise vs. Input Range and Update Rate (CHP = 1)
Typical Output RMS Noise in nV
*Power-On Default
Table II.Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1)
Peak-to-Peak Resolution in Counts (Bits)
*Power-On Default
Output Noise (CHP = 0)
Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730 when used in non-
chopping mode (CHP of Filter Register = 0) with a master clock frequency of 4.9152 MHz. These numbers are typical and are gen-
erated at a differential analog input voltage of 0 V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register.
Table IV, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. The numbers in brackets
are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB). It is important to note that the numbers in Table
IV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms
noise, but on peak-to-peak noise.
The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in Table III will remain the same for unipolar ranges while the
Table III.Output Noise vs. Input Range and Update Rate (CHP = 0)
Typical Output RMS Noise in nV
Table IV.Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0)
Peak-to-Peak Resolution in Counts (Bits)
ON-CHIP REGISTERS
The AD7730 contains thirteen on-chip registers which can be accessed via the serial port of the part. These registers are summarized
in Figure 4 and in Table V and described in detail in the following sections.
COMMUNICATIONS REGISTER
DIN
DOUT
DOUT
Figure 4.Register Overview
AD7730/AD7730L
Table V.Summary of On-Chip Registers
Power-On/Reset
Register NameTypeSizeDefault ValueFunction
CommunicationsWrite Only8 BitsNot ApplicableAll operations to other registers are initiated through
Registerthe Communications Register. This controls whether
subsequent operations are read or write operations
and also selects the register for that subsequent
operation. Most subsequent operations return con-
trol to the Communications Register except for the
continuous read mode of operation.
Status RegisterRead Only8 BitsCX HexProvides status information on conversions, calibra-
tions, settling to step inputs, standby operation and
the validity of the reference voltage.
Data RegisterRead Only16 Bits or 24 Bits000000 HexProvides the most up-to-date conversion result from
the part. Register length can be programmed to be
16 bits or 24 bits.
Mode RegisterRead/Write16 Bits01B0 HexControls functions such as mode of operation, uni-
polar/bipolar operation, controlling the function of
AIN2(+)/D1 and AIN2(-)/D0, burnout current,
Data Register word length and disabling of MCLK
OUT. It also contains the reference selection bit, the
range selection bits and the channel selection bits.
Filter RegisterRead/Write24 Bits200010 HexControls the amount of averaging in the first stage
filter, selects the fast step and skip modes and con-
trols the ac excitation and chopping modes on the
part.
DAC RegisterRead/Write8 Bits20 HexProvides control of the amount of correction per-
formed by the Offset/TARE DAC.
Offset RegisterRead/Write24 Bits800000 HexContains a 24-bit word which is the offset calibration
coefficient for the part. The contents of this register
are used to provide offset correction on the output
from the digital filter. There are three Offset Regis-
ters on the part and these are associated with the
input channels as outlined in Table XIII.
Gain RegisterRead/Write24 Bits59AEE7 HexContains a 24-bit word which is the gain calibration
coefficient for the part. The contents of this register
are used to provide gain correction on the output
from the digital filter. There are three Gain Registers
on the part and these are associated with the input
channels as outlined in Table XIII.
Test RegisterRead/Write24 Bits000000 HexControls the test modes of the part which are used
when testing the part. The user is advised not to
change the contents of this register.
Communications Register (RS2–RS0 = 0, 0, 0)
The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the
Communications Register. The data written to the Communications Register determines whether the next operation is a read or
write operation, the type of read operation, and to which register this operation takes place. For single-shot read or write operations,
once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write op-
eration to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7730
is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is
lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7730 to this default state by resetting the
part. Table VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denot-
ing the bits are in the Communications Register. CR7 denotes the first bit of the data stream.
Table VI.Communications Register
CR6
CR5, CR4
AD7730/AD7730L
CR2–CR0
Table VIII.Register Selection
Status Register (RS2–RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex
The Status Register is an 8-bit read-only register. To access the Status Register, the user must write to the Communications Register
selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig-
nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7
denotes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7730. The number
in brackets indicates the power-on/reset default status of that bit.
Table IX.Status Register
Data Register (RS2–RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex
The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7730. Fig-
ure5 shows a flowchart for reading from the registers on the AD7730. The register can be programmed to be either 16 bits or 24bits
wide, determined by the status of the WL bit of the Mode Register. The RDY output and RDY bit of the Status Register are set low
when the Data Register is updated. The RDY pin and RDY bit will return high once the full contents of the register (either 16bits orbits) have been read. If the Data Register has not been read by the time the next output update occurs, the RDY pin and RDY bit
will go high for at least 100 × tCLK IN, indicating when a read from the Data Register should not be initiated to avoid a transfer from
the Data Register as it is being updated. Once the updating of the Data Register has taken place, RDY returns low.
If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place
in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the inter-
face). However, the 16 or 24 bits of data written to the part will be ignored by the AD7730.
Mode Register (RS2–RS0 = 0, 1, 0); Power On/Reset Status: 01B0Hex
The Mode Register is a 16-bit register from which data can be read or to which data can be written. This register configures
the operating modes of the AD7730, the input range selection, the channel selection and the word length of the Data Register.
TableX outlines the bit designations for the Mode Register. MR0 through MR15 indicate the bit location, MR denoting the bits are
in the Mode Register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default
status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writ-
ing to the registers on the part.
Table X.Mode Register
Table XI.Operating Modes
AD7730/AD7730L

AD7730/AD7730L
Table XIII.Channel Selection
Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 200010Hex
The Filter Register is a 24-bit register from which data can be read or to which data can be written. This register determines the
amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode and the delay
associated with chopping the inputs. Table XIV outlines the bit designations for the Filter Register. FR0 through FR23 indicate the
bit location, FR denoting the bits are in the Filter Register. FR23 denotes the first bit of the data stream. The number in brackets
indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and
Figure 6 shows a flowchart for writing to the registers on the part.
Table XV.SF Ranges
AD7730/AD7730L
DAC Register (RS2–RS0 = 1, 0, 0); Power On/Reset Status: 20Hex
The DAC Register is an 8-bit register from which data can either be read or to which data can be written. This register provides
the code for the offset-compensation DAC on the part. Table XVI outlines the bit designations for the DAC Register. DR0
through DR7 indicate the bit location, DR denoting the bits are in the DAC Register. DR7 denotes the first bit of the data
stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading
from the registers on the AD7730 and Figure 6 shows a flowchart for writing to the registers on the part.
Table XVI.DAC Register
Offset Calibration Register (RS2–RS0 = 1, 0, 1); Power-On/Reset Status: 800000Hex
The AD7730 contains three 24-bit Offset Calibration Registers, labelled Offset Calibration Register 0 to Offset Calibration Reg-
ister2, to which data can be written and from which data can be read. The three registers are totally independent of each other.
The Offset Calibration Register is used in conjunction with the associated Gain Calibration Register to form a register pair. The
calibration register pair used to scale the output is as outlined in Table XIII. The Offset Calibration Register is updated after an
offset calibration routine (1, 0, 0 or 1, 1, 0 loaded to the MD2, MD1, MD0 bits of the Mode Register). During subsequent
conversions, the contents of this register are subtracted from the filter output prior to gain scaling being performed on the word.
Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writing to the regis-
ters on the part.
Gain Calibration Register (RS2–RS0 = 1, 1, 0); Power-On/Reset Status: 593CEA
The AD7730 contains three 24-bit Gain Calibration Registers, labelled Gain Calibration Register 0 to Gain Calibration Register
2, to which data can be written and from which data can be read. The three registers are totally independent of each other. The
Gain Calibration Register is used in conjunction with the associated Offset Calibration Register to form a register pair. The
calibration register pair used to scale the output is as outlined in Table XIII. The Gain Calibration Register is updated after a
gain calibration routine (1, 0, 1 or 1, 1, 1 loaded to the MD2, MD1, MD0 bits of the Mode Register). During subsequent con-
versions, the contents of this register are used to scale the number which has already been offset corrected with the Offset Cali-
bration Register contents. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a
flowchart for writing to the registers on the part.
Test Register (RS2–RS0 = 1, 1, 1); Power-On/Reset Status: 000000Hex
The AD7730 contains a 24-bit Test Register to which data can be written and from which data can be read. The contents of this
Test Register are used in testing the device. The user is advised not to change the status of any of the bits in this register from the
default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly. If the
part enters one of its test modes, exercising RESET or writing 32 successive 1s to the part will exit the AD7730 from the mode and
return all register contents to their power-on/reset status. Note, if the part is placed in one of its test modes, it may not be possible to
read back the contents of the Test Register depending on the test mode in which the part has been placed.
READING FROM AND WRITING TO THE ON-CHIP REGISTERS
The AD7730 contains a total of thirteen on-chip registers. These registers are all accessed over a three-wire interface. As a result,
addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a
flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of
the registers. Figure 6 gives a flowchart for writing to the different registers on the part, again summarizing the sequence and words
to be written to the AD7730.
Figure 5.Flowchart for Reading from the AD7730 Registers
*N/A= Not Applicable. Continuous reads of these registers does not make sense
as the register contents would remain the same since they are only changed by a
write operation.
START
AD7730/AD7730L
CALIBRATION OPERATION SUMMARY
The AD7730 contains a number of calibration options as outlined previously. Table XVII summarizes the calibration types, the
operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to
monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method is to do a software poll of the
RDY bit in the Status Register. This can be achieved by setting up the part for continuous reads of the Status Register once a calibra-
tion has been initiated. The RDY pin and RDY bit go high on initiating a calibration and return low at the end of the calibration
routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. The FAST and SKIP bits are treated
as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full detail.
Table XVII.Calibration Operations
System Zero-Scale
CIRCUIT DESCRIPTION
The AD7730 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low-frequency signals such as those in weigh-scale, strain-gage,
pressure transducer or temperature measurement applications.
It contains a sigma-delta (or charge-balancing) ADC, a calibra-
tion microcontroller with on-chip static RAM, a clock oscillator,
a digital filter and a bidirectional serial communications port.
The part consumes 13mA of power supply current with a standby
mode which consumes only 25μA. The part operates from a single
+5 V supply. The clock source for the part can be provided via an
external clock or by connecting a crystal oscillator or ceramic
resonator across the MCLKIN and MCLKOUT pins.
The part contains two programmable-gain fully differential analog
input channels. The part handles a total of eight different input
ranges which are programmed via the on-chip registers. There are
four differential unipolar ranges:0 mV to +10mV, 0 mV to
+20mV, 0 mV to +40mV and 0 mV to +80mV and four differen-
tial bipolar ranges: ±10mV, ±20mV, ±40mV and ±80mV.
The AD7730 employs a sigma-delta conversion technique to
realize up to 24 bits of no missing codes performance. The
sigma-delta modulator converts the sampled input signal into a
digital pulse train whose duty cycle contains the digital informa-
tion. A digital low-pass filter processes the output of the sigma-
delta modulator and updates the data register at a rate that can
be programmed over the serial interface. The output data from
the part is accessed over this serial interface. The cutoff frequency
and output rate of this filter can be programmed via on-chip
registers. The output noise performance and peak-to-peak reso-
lution of the part varies with gain and with the output rate as
shown in Tables I to IV.
The analog inputs are buffered on-chip allowing the part to
handle significant source impedances on the analog input. This
means that external R, C filtering (for noise rejection or RFI
reduction) can be placed on the analog inputs if required. Both
analog channels are differential, with a common-mode voltage
range that comes within 1.2V of AGND and 0.95V of AVDD.
The reference input is also differential and the common-mode
range here is from AGND to AVDD.
The part contains a 6-bit DAC that is controlled via on-chip
registers. This DAC can be used to remove TARE values of up
to ±80mV from the analog input signal range. The resolution
on this TARE function is 1.25mV for a +2.5 V reference and
2.5 mV with a +5 V reference.
The AD7730 can accept input signals from a dc-excited bridge.
It can also handle input signals from an ac-excited bridge by
using the ac excitation clock signals (ACX and ACX) to switch
the supplies to the bridge. ACX and ACX are nonoverlapping
clock signals used to synchronize the external ac supplies that
drive the transducer bridge. These ACX clocks are demodulated
on the AD7730 input.
The AD7730 contains a number of hardware and software
events that set or reset status flags and bits in registers. Table
XVIII summarizes which blocks and flags are affected by the
different events.
Table XVIII.Reset Events
AD7730/AD7730L
ANALOG INPUT
Analog Input Channels
The AD7730 contains two differential analog input channels, a
primary input channel, AIN1, and a secondary input channel,
AIN2. The input pairs provide programmable gain, differential
channels which can handle either unipolar or bipolar input
signals. It should be noted that the bipolar input signals are
referenced to the respective AIN(–) input of the input pair. The
secondary input channel can also be reconfigured as two digital
output port bits.
A two-channel differential multiplexer switches one of the two
input channels to the on-chip buffer amplifier. This multiplexer
is controlled by the CH0 and CH1 bits of the Mode Register.
When the analog input channel is switched, the RDY output
goes high and the settling time of the part must elapse before a
valid word from the new channel is available in the Data Regis-
ter (indicated by RDY going low).
Buffered Inputs
The output of the multiplexer feeds into a high impedance input
stage of the buffer amplifier. As a result, the analog inputs can
handle significant source impedances. This buffer amplifier has
an input bias current of 50nA (CHP = 1) and 60nA (CHP = 0).
This current flows in each leg of the analog input pair. The
offset current on the part is the difference between the input
bias on the legs of the input pair. This offset current is less thannA (CHP = 1) and 30 nA (CHP = 0). Large source resis-
tances result in a dc offset voltage developed across the source
resistance on each leg, but matched impedances on the analog
input legs will reduce the offset voltage to that generated by the
input offset current.
Analog Input Ranges
The absolute input voltage range is restricted to between
AGND+ 1.2V to AVDD – 0.95V, which also places restrictions
on the common-mode range. Care must be taken in setting up
the common-mode voltage and input voltage range so these
limits are not exceeded, otherwise there will be a degradation in
linearity performance.
In some applications, the analog input range may be biased
either around system ground or slightly below system ground. In
such cases, the AGND of the AD7730 must be biased negative
with respect to system ground so the analog input voltage does
not go within 1.2 V of AGND. Care should taken to ensure that
the differential between either AVDD or DVDD and this biased
AGND does not exceed 5.5V. This is discussed in more detail
in the Applications section.
Programmable Gain Amplifier
The output from the buffer amplifier is summed with the output
of the 6-bit Offset DAC before it is applied to the input of the
on-chip programmable gain amplifier (PGA). The PGA can
handle four different unipolar input ranges and four bipolar
ranges. With the HIREF bit of the Mode Register at 0 and a
+2.5V reference (or the HIREF bit at 1 and a +5V reference),
the unipolar ranges are 0 mV to +10mV, 0 mV to +20mV,
0 mV to +40mV, and 0 mV to +80mV, while the bipolar ranges
are ±10mV, ±20mV, ±40mV and ±80mV. These are the
nominal ranges that should appear at the input to the on-chip
Offset DAC
The purpose of the Offset DAC is to either add or subtract an
offset so the input range at the input to the PGA is as close as
possible to the nominal. If the output of the 6-bit Offset DAC isV, the differential voltage ranges that appear at the analog
input to the part will also appear at the input to the PGA. If,
however, the Offset DAC has an output voltage other than 0V,
the input range to the analog inputs will differ from that applied
to the input of the PGA.
The Offset DAC has five magnitude bits and one sign bit. The
sign bit determines whether the value loaded to the five magni-
tude bits is added to or subtracted from the voltage at the ana-
log input pins. Control of the Offset DAC is via the DAC
Register which is discussed previously in the On-Chip Registers
section. With a 5V reference applied between the REFIN pins,
the resolution of the Offset DAC is 2.5mV with a range that
allows addition or subtraction of 77.5mV. With a 2.5V refer-
ence applied between the REFIN pins, the resolution of the
Offset DAC is 1.25mV with a range that allows addition or
subtraction of 38.75mV.
Following is an example of how the Offset DAC works. If the
differential input voltage range the user had at the analog input
pins was +20 mV to +30mV, the Offset DAC should be pro-
grammed to subtract 20mV of offset so the input range to the
PGA is 0 mV to +10mV. If the differential input voltage range
the user had at the analog input pins was –60 mV to +20mV,
the Offset DAC should be programmed to add 20mV of offset so
the input range to the PGA is ±40mV.
Bipolar/Unipolar Inputs
The analog inputs on the AD7730 can accept either unipolar or
bipolar input voltage ranges. Bipolar input ranges do not imply
that the part can handle negative voltages with respect to system
ground on its analog inputs unless the AGND of the part is also
biased below system ground. Unipolar and bipolar signals on
the AIN(+) input are referenced to the voltage on the respective
AIN(–) input. For example, if AIN(–) is +2.5V and the AD7730 is
configured for an analog input range of 0 to +10mV with no
DAC offset correction, the input voltage range on the AIN(+)
input is +2.5V to +2.51V. Similarly, if AIN(–) is +2.5V and the
AD7730 is configured for an analog input range of ±80mV
with no DAC offset correction, the analog input range on the
AIN(+) input is +2.42V to +2.58 V (i.e., 2.5V ± 80mV).
Bipolar or unipolar options are chosen by programming the B/U
bit of the Mode Register. This programs the selected channel
for either unipolar or bipolar operation. Programming the chan-
nel for either unipolar or bipolar operation does not change any
of the input signal conditioning; it simply changes the data
output coding and the points on the transfer function where
calibrations occur. When the AD7730 is configured for unipolar
operation, the output coding is natural (straight) binary with a
zero differential voltage resulting in a code of 000...000, a
midscale voltage resulting in a code of 100...000 and a full-
scale input voltage resulting in a code of 111...111. When the
AD7730 is configured for bipolar operation, the coding is offset
binary with a negative full scale voltage resulting in a code of
000...000, a zero differential voltage resulting in a code of
Burnout Currents
The AD7730 contains two 100nA constant current generators,
one source current from AVDD to AIN(+) and one sink current
from AIN(–) to AGND. The currents are switched to the se-
lected analog input pair. Both currents are either on or off,
depending on the BO bit of the Mode Register. These currents
can be used in checking that a transducer is still operational
before attempting to take measurements on that channel. If the
currents are turned on, allowed flow in the transducer, a mea-
surement of the input voltage on the analog input taken and the
voltage measured is full scale, it indicates that the transducer
has gone open-circuit. If the voltage measured is 0 V, it indicates
that the transducer has gone short circuit. For normal operation,
these burnout currents are turned off by writing a 0 to the BO
bit. The current sources work over the normal absolute input
voltage range specifications.
REFERENCE INPUT
The AD7730’s reference inputs, REFIN(+) and REFIN(–),
provide a differential reference input capability. The common-
mode range for these differential inputs is from AGND to
AVDD. The nominal reference voltage, VREF (REFIN(+)—
REFIN(–)), for specified operation is +2.5V with the HIREF
bit at 0 V and +5V with the HIREF bit at 1. The part is also
functional with VREF of +2.5V with the HIREF bit at 1. This
results in a halving of all input ranges. The resolution in nV will
be unaltered but will appear halved in terms of counts.
Both reference inputs provide a high impedance, dynamic load.
The typical average dc input leakage current over temperature
is 8.5μA with HIREF=1 and VREF=+5V, and 2.5μA with
HIREF=0 and VREF=+2.5V. Because the input impedance of
each reference input is dynamic, external resistance/capacitance
combinations on these inputs may result in gain errors on the
part.
The AD7730 can be operated in either ac or dc mode. If the
bridge excitation is fixed dc, the AD7730 should be operated in
dc mode. If the analog input and the reference inputs are externally
chopped before being applied to the part the AD7730 should be
operated in ac mode and not dc mode. In ac mode, it is assumed
that both the analog inputs and reference inputs are chopped
and as a result change phase every alternate chopping cycle. If
the chopping is synchronized by the AD7730 (using the ACX
signals to control the chopping) the part then takes into account
the reversal of the analog input and reference input signals.
The output noise performance outlined in Tables I through IV
is for an analog input of 0V and is unaffected by noise on the
reference. To obtain the same noise performance as shown in
the noise tables over the full input range requires a low noise
reference source for the AD7730. If the reference noise in the
bandwidth of interest is excessive, it will degrade the performance
of the AD7730. In applications where the excitation voltage for
the bridge transducer on the analog input also drives the refer-
ence voltage for the part, the effect of the noise in the excita-
tion voltage will be removed as the application is ratiometric.
Figure 7 shows how the reference voltage can be connected in a
ratiometric fashion in a dc-excited bridge application. In this
case, the excitation voltage for the AD7730 and the transducer
Figure 7.Ratiometric Generation of Reference in DC-
Excited Bridge ApplicationDGND
Figure 8.Ratiometric Generation of Reference in AC-
Excited Bridge Application
application. In this case, both the reference voltage for the part
and the excitation voltage for the transducer are chopped. Once
again, the HIREF bit should be set to 1.
If the AD7730 is not used in a ratiometric application, a low
noise reference should be used. Recommended 2.5 V reference
voltage sources for the AD7730 include the AD780, REF43
and REF192. If any of these references are used as the reference
source for the AD7730, the HIREF bit should be set to 0. It is
generally recommended to decouple the output of these references
to further reduce the noise level.
Reference Detect
The AD7730 includes on-chip circuitry to detect if the part
has a valid reference for conversions or calibrations. If the volt-
age between the REF IN(+) and REF IN(–) pins goes below
0.3V or either the REF IN(+) or REF IN(–) inputs is open
circuit, the AD7730 detects that it no longer has a valid reference.
In this case, the NO REF bit of the Status Register is set to a 1.
If the AD7730 is performing normal conversions and the NO
REF bit becomes active, the part places all ones in the Data
Register. Therefore, it is not necessary to continuously monitor
the status of the NO REF bit when performing conversions. It is
only necessary to verify its status if the conversion result read
from the Data Register is all 1s.
AD7730/AD7730L
If the AD7730 is performing either an offset or gain calibration
and the NOREF bit becomes active, the updating of the respec-
tive calibration register is inhibited to avoid loading incorrect
coefficients to this register. If the user is concerned about verify-
ing that a valid reference is in place every time a calibration is
performed, then the status of the NOREF bit should be checked
at the end of the calibration cycle.
SIGMA-DELTA MODULATOR
A sigma-delta ADC generally consists of two main blocks, an
analog modulator and a digital filter. In the case of the AD7730,
the analog modulator consists of a difference amplifier, an inte-
grator block, a comparator and a feedback DAC as illustrated in
Figure 9. In operation, the analog signal sample is fed to the
difference amplifier along with the output of the feedback DAC.
The difference between these two signals is integrated and fed to
the comparator. The output of the comparator provides the
input to the feedback DAC so that the system functions as a
negative feedback loop that tries to minimize the difference
signal. The digital data that represents the analog input voltage
is contained in the duty cycle of the pulse train appearing at the
output of the comparator. This duty cycle data can be recovered
as a data word using the digital filter. The sampling frequency of
the modulator loop is many times higher than the bandwidth of
the input signal. The integrator in the modulator shapes the
quantization noise (which results from the analog-to-digital
conversion) so that the noise is pushed toward one half of the
modulator frequency. The digital filter then bandlimits the re-
sponse to a frequency significantly lower than one half of the
modulator frequency. In this manner, the 1-bit output of the
comparator is translated into a bandlimited, low noise output
from the AD7730.
ANALOG
INPUT
DIFFERENCE
AMPCOMPARATOR
DIGITAL DATA
Figure 9.Sigma-Delta Modulator Block Diagram
DIGITAL FILTERING
Filter Architecture
The output of the modulator feeds directly into the digital filter.
This digital filter consists of two portions, a first stage filter and
a second stage filter. The first stage filter is a sinc3, low-pass
filter. The cutoff frequency and output rate of this first stage
filter is programmable. The second stage filter has three distinct
modes of operation. In its normal mode, it provides a low-pass
FIR filter that processes the output of the first stage filter. When
a step change is detected on the analog input, this second stage
filter enters a second mode where it performs a variable number
of averages for some time after the step change and then the
second stage filter switches back to the FIR filter. The third
option for the second stage filter is that it is completely bypassed
so the only filtering provided on the AD7730 is the first stage.
The various filter stages and options are discussed in the follow-
First Stage Filter
The first stage filter is a low-pass, sinc3 or (sinx/x)3 filter whose
primary function is to remove the quantization noise introduced
at the modulator. The cutoff frequency and output rate of this
filter is programmed via the SF0 to SF11 bits of the Filter Reg-
ister. The frequency response for this first stage filter is shown in
Figure 10. The response of this first stage filter is similar to that
of an averaging filter but with a sharper roll-off. The output rate
for the filter corresponds with the positioning of the first notch
of the filter’s frequency response. Thus, for the plot of Figure 10,
where the output rate is 600Hz (fCLK IN = 4.9152 MHz and
SF = 512), the first notch of the filter is at 600Hz. The notches
of this sinc3 filter are repeated at multiples of the first notch. The
filter provides attenuation of better than 100dB at these notches.
Programming a different cutoff frequency via SF0 – SF11 does
not alter the profile of the filter response; it changes the fre-
quency of the notches as outlined in the Filter Registers section.
This response is repeated at either side of the input sampling
frequency (307 kHz) and at either side of multiples of the input
sampling frequency.
FREQUENCY – Hz
GAIN – dB
–110
Figure 10.Frequency Response of First Stage Filter
The first stage filter has two basic modes of operation. The
primary mode of operation for weigh-scale applications is chop
mode, which is achieved by placing a 1 in the CHP bit of the
Filter Register. The part should be operated in this mode when
drift and noise rejection are important criteria in the application.
The alternative mode of operation is the nonchop mode, with
CHP at 0, which would be used when higher throughput rates
are a concern or in applications where the reduced rejection at
the chopping frequency in chop mode is an issue.
Nonchop Mode
With chop mode disabled on the AD7730, the first stage filter
continuously processes input data and produces a result at an
output rate determined by the SF word. Operating in nonchop
mode can result in a 20% reduction in noise for a given band-
width, but without the excellent drift and noise rejection ben-
efits which accrue from chopping the part. The output update
and first notch of this first stage filter correspond and are deter-
mined by the relationship:

Partno	Mfg	Dc	Qty	Available	Descript
AD7730BN	AD	N/a	4	avai	Bridge Transducer ADC
AD7730BRU	AD	N/a	8	avai	Bridge Transducer ADC