AD7729ARU Fast Delivery |IC PHOENIX CO.,LIMITED

AD7729ARU ,Dual Sigma-Delta ADC with Auxiliary DACSpecifications Input Frequency = 67.7 kHzDynamic Range 67 dB typSignal to (Noise + Distortion) 64 d ..
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AD7729ARU
Dual Sigma-Delta ADC with Auxiliary DAC
REV.0
Dual Sigma-Delta ADC
with Auxiliary DAC
FUNCTIONAL BLOCK DIAGRAM
ASDI
ASDIFS
ASCLK
ASDO
ASDOFS
ASE
BSDI
BSDIFS
BSCLK
BSDO
BSDOFS
BSE
MCLK
RxON
RESETB
AUXDAC
IRxP
IRxN
QRxP
QRxN
REFCAP
REFOUT
AVDD2AVDD1DGNDDVDD1DVDD2AGND
FEATURES
+3 V Supply Voltage
Baseband Serial Port (BSPORT)
Differential IRx and QRx
ADC Channels
Two 15-Bit Sigma-Delta A/D Converters
FIR Digital Filters
64 dB SNR
Output Word Rate 270.83 kHz
Twos Complement Coding
On-Chip Offset Calibration
Power-Down Mode
Auxiliary D/A Converter
Auxiliary Serial Port (ASPORT)
On-Chip Voltage Reference
Low Power
28-Lead TSSOP/28-Lead SOIC
APPLICATIONS
GSM Basestations
Pagers
GENERAL DESCRIPTION
This monolithic 3 V CMOS device is a low power, two-channel,
input port with signal conditioning. The receive path is com-
posed of two high performance sigma-delta ADCs with digital
filtering. A common bandgap reference feeds the ADCs.
A control DAC is included for such functions as AFC. The auxil-
iary functions can be accessed via the auxiliary port (ASPORT).
This device is available in a 28-lead TSSOP package or a
28-lead SOIC package.
AD7729–SPECIFICATIONS1
AUXILIARY CONVERTER
(AVDD1 = AVDD2 = +3 V 6 10%; DVDD1 = DVDD2 = +3 V 6 10%; DGND = AGND =V, fCLK = 13 MHz; RxPOWER1 = 0; RxPOWER0 = 1; MCLKDIV = 0; TA = TMIN to TMAX unless otherwise noted)
AD7729
LOGIC OUTPUTS
POWER SUPPLIES
NOTESOperating Temperature Range: –40°C to +105°C. Therefore, TMIN = –40°C and TMAX = +105°C.During power-down, the AUXDAC has an output resistance of 30 kW approximately to AGND.
Specifications subject to change without notice.
Table I.Current Summary (AVDD1 = AVDD2 = DVDD1 = DVDD2 = +3.3 V, RxPOWER1 = 0, RxPOWER0 = 1)
The above values are in mA.
Figure 1.AUXDAC Load Equivalent Circuit
AD7729
TIMING CHARACTERISTICS
t10
t11
t12
t13
t14
t15
t16
t18
t19
t20
t21
t22
t23
t24
ASCLK = MCLK/(2 · ASCLKRATE). ASCLKRATE can have a value from 0...1023. When ASCLKRATE = 0, ASCLK = 13 MHz.
BSCLK = MCLK/(2 · BSCLKRATE). BSCLKRATE can have a value from 0...1023. When BSCLKRATE = 0, BSCLK = 13 MHz.
Specifications subject to change without notice.
(AVDD1 = AVDD2 = +3 V 6 10%; DVDD1 = DVDD2 = +3 V 6 10%; AGND = DGND = 0 V;
TA = TMIN to TMAX, unless otherwise noted)
Table II.Receive Section Signal Ranges
Table III.Auxiliary Section Signal Ranges
TIMING DIAGRAMS
ASE (I)
ASCLK (O)
ASDIFS (I)
ASDOFS (O)
ASDI (I)
ASDO (O)
THREE-STATE
THREE-STATE
THREE-STATE
NOTE
I = INPUT, O = OUTPUT
Figure 6.Auxiliary Serial Port ASPORT
BSE (I)
BSCLK (O)
BSDIFS (I)
BSDOFS (O)
BSDI (I)
BSDO (O)
NOTE
I = INPUT, O = OUTPUT
Figure 2.Clock Timing
Figure 3.Load Circuit for Timing Specifications
Figure 4.ASCLK
Figure 5.BSCLK
AD7729
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise stated)
AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
TSSOP
qJA Thermal Impedance . . . . . . . . . . . . . . . . . . . +122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SOIC
qJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . +72°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7729 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
AD7729
TERMINOLOGY
Absolute Group Delay
Absolute group delay is the rate of change of phase versus fre-
quency, dø/df. It is expressed in microseconds.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the DAC or
ADC.
Dynamic Range
Dynamic Range is the ratio of the maximum output signal to the
smallest output signal the converter can produce (1 LSB), ex-
pressed logarithmically, in decibels (dB = 201og10 (ratio)). For
an N-bit converter, the ratio is theoretically very nearly equal toN (in dB, 20Nlog10(2) = 6.02N). However, this theoretical
value is degraded by converter noise and inaccuracies in the
LSB weight.
Gain Error
This is a measure of the output error between an ideal DAC and
the actual device output with all 1s loaded after offset error has
been adjusted out. In the AD7729, gain error is specified for the
auxiliary section.
Gain Matching Between Channels
This is the gain matching between the IRx and QRx channel
and is expressed in dBs.
Group Delay Between Channels
This is the difference between the group delay of the I and Q
channels and is a measure of the phase matching characteristics
of the two.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the auxiliary DAC transfer function.
Output Rate
This is the rate at which data words are made available
(270.833 kHz).
Offset Error
This is the amount of offset, wrt VREF in the auxiliary DAC and
is expressed in mVs.
Output Signal Span
This is the output signal range for the auxiliary DAC section.
Sampling Rate
This is the rate at which the modulators on the receive channels
sample the analog input.
Settling Time
This is the digital filter settling time in the AD7729 receive
section. On initial power-up or after returning from the power-
down mode, it is necessary to wait this amount of time to get
useful data.
Signal Input Span
The input signal range for the I and Q channels is biased about
VREF.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the receive channel. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for a sine wave is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Partno	Mfg	Dc	Qty	Available	Descript
AD7729ARU	AD	N/a	5311	avai	Dual Sigma-Delta ADC with Auxiliary DAC
AD7729ARU	ADI	N/a	161	avai	Dual Sigma-Delta ADC with Auxiliary DAC