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AD7725BS
16-Bit Sigma Delta ADC with a Programmable Post Processor
REV.A
16-Bit 900 kSPS �-� ADC with a
Programmable Postprocessor
FEATURES
Programmable Filtering:
Any Characteristic up to 108 Tap FIR and/or IIR
Polynomial Signal Conditioning up to 8th Order
Programmable Decimation and Output Word Rate
Flexible Programming Modes:
Boot from DSP or External EPROM
Parallel/Serial Interface
Internal Default Filter for Evaluation
14.4 MHz Max Master Clock Frequency
0 V to +4 V (Single-Ended) or �2 V (Differential) Input
Range
Power Supplies: AVDD, DVDD: 5 V � 5%
On-Chip 2.5 V Voltage Reference
44-Lead MQFP Package
TYPICAL APPLICATIONS
Radar
Sonar
Auxiliary Car Functions
Medical Communications
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD7725 is a complete 16-bit, �-� analog-to-digital con-
verter with on-chip, user-programmable signal conditioning. The
output of the modulator is processed by three cascaded finite
impulse response (FIR) filters, followed by a fully user-program-
mable postprocessor. The postprocessor provides processing
power of up to 130 million accumulates (MAC) per second. The
user has complete control over the filter response, the filter coeffi-
cients, and the decimation ratio.
The postprocessor permits the signal conditioning characteris-
tics to be programmed through a parallel or serial interface. It
is programmed by loading a user-defined filter in the form of a
configuration file. This filter can be loaded from a DSP or an
external serial EPROM. It is generated using a digital filter
design package called Filter Wizard, which is available from the
AD7725 section on the Analog Devices website.
Filter Wizard allows the user to design different filter types
and generates the appropriate configuration file to be down-
loaded to the postprocessor. The AD7725 also has an internal
default filter for evaluation purposes.
It provides 16-bit performance for input bandwidths up to
350 kHz with an output word rate of 900 kHz maximum. The
input sample rate is set either by the crystal oscillator or an
external clock.
This part has an accurate on-chip 2.5 V reference for the modu-
lator. A reference input/output function allows either the
internal reference or an external system reference to be used as
the reference source for the modulator.
The device is available in a 44-lead MQFP package and is speci-
fied over a –40°C to +85°C temperature range.
AD7725–SPECIFICATIONS1(AVDD = 5 V � 5%, AGND = AGND1 = AGND2 = DGND = 0 V,
fCLKIN2 = 9.6 MHz, REF2 = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.)ANALOG INPUTS
STATIC PERFORMANCE
CLOCK INPUT (CLKIN)
AD7725LOGIC OUTPUTS
NOTESOperating temperature range is as follows: B Version: –40°C to +85°C.fCLKIN is the CLKIN frequency.See Terminology section.FO = output data rate.When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 µF decoupling capacitor between REF2 and
AGND2. At frequencies below 10 kHz, THD degrades to –80 dB and SFDR degrades to –83 dB.See Figures 23 and 24 for information regarding the number of filter taps allowed and the current consumption as the CLKIN frequency is varied.The AD7725 can operate with an external reference input in the range of 1.2 V to 3.15 V.Guaranteed by the design.Gain Error excludes reference error.All IDD tests are done with the digital inputs equal to 0 V or DVDD.Analog current does not vary as the CLKIN frequency and the number of filter taps used in the postprocessor is varied.If HALF_PWR is logic low, AIDD will typically double.Digital current varies as the CLKIN frequency and the number of filter taps used in the postprocessor is varied. See Figures 23 and 24.Digital inputs static and equal to 0 V or DVDD.
Specifications subject to change without notice.
Figure 1.Digital Filter Characteristics Used for Specifications
AD7725
Preset Filter, Default Filter, and Postprocessor Characteristics1, 2DEFAULT FILTER
POSTPROCESSOR CHARACTERISTICS
NOTESThese characteristics are fixed by the design.fCLKIN is the CLKIN frequency.See Terminology section.See the Configuration File Format section for more information.
AD7725CLKIN Period (tCLK = 1/fCLKIN)t1
CLKIN Fall Time
CLKIN to SCO Delay
SCO Period:
SERIAL INTERFACE (DSP AND BFR MODES)
SERIAL INTERFACE (EPROM MODE)
PARALLEL INTERFACE
NOTESGuaranteed by design.Guaranteed by characterization. All input signals are specified with tr � tf � 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V and 2.4 V.
TIMING SPECIFICATIONS1, 2(AVDD = 5 V � 5%; DVDD = 5 V � 5%; AGND = DGND = 0 V, REF2=2.5 V,
unless otherwise noted.)
AD7725Figure 2.Load Circuit for Digital Output Timing Specifications
Figure 3.CLKIN to SCO Relationship
Figure 4.Serial Mode (DSP Mode and Boot from ROM (BFR) Mode). In BFR Mode, FSI and SDI are not used.
Figure 5.Serial Mode (EPROM Mode)
Figure 6.Parallel Mode (Writing Data to the AD7725)
Figure 7.Parallel Mode (Reading Data from the AD7725)
AD7725
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C, unless otherwise noted.)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD, AVDD1 to DVDD . . . . . . . . . . . . . . . . . . . .–1 V to +1 V
AGND, AGND1 to DGND . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital Inputs to DGND . . . . . . . . . .–0.3 V to DVDD + 0.3 V
Digital Outputs to DGND . . . . . . . . .–0.3 V to DVDD + 0.3 V
VIN(+), VIN(–) to AGND . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
REF1 to AGND . . . . . . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
REF2 to AGND . . . . . . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
DGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±0.3 V
Input Current to Any Pin except Supplies2 . . . . . . . . .±10 mA
IDD (AIDD + DIDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 mA
Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . .58°C/W
�JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . .20°C/W
Lead Temperature, Soldering
Vapor Phase (60sec) . . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 kV
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDEAD7725BS-REEL
EVAL-
EVAL-
CONTROL
NOTESS = Metric Quad Flat Package (MQFP).This board can be used as a standalone evaluation board or in conjunction with the
Evaluation Board Controller for evaluation/demonstration purposes. It is accom-
panied by software and technical documentation.Evaluation Board Controller. This board is a complete unit allowing a PC to
control and communicate with all Analog Devices boards ending in the CB
designator. To obtain the complete evaluation kit, the following needs to be
ordered: EVAL-AD7725CB, EVAL-CONTROL BRD2, and a 12 V ac transformer.
The Filter Wizard software can be downloaded from the Analog Devices website.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
Figure 8.Parallel Mode (Reading the Status Register and Writing Instructions)
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
AD772516, 18
AD7725TERMINOLOGY
Integral Nonlinearity (INL)This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be
confused with bipolar zero), a point 0.5 LSB below the first
code transition (100...00 to 100...01 in bipolar mode,
000...00 to 000...01 in unipolar mode) and full scale, a
point 0.5 LSB above the last code transition (011...10 to
011...11 in bipolar mode, 111...10 to 111...11 in
unipolar mode). The error is expressed in LSBs.
Differential Nonlinearity (DNL)This is the difference between the measured and the ideal
1LSB change between two adjacent codes in the ADC.
Unipolar Offset ErrorUnipolar offset error is the deviation of the first code transition
from the ideal VIN(+) voltage, which is (VIN(–) + 0.5 LSB) when
operating in the unipolar mode.
Bipolar Offset ErrorThis is the deviation of the midscale transition code
(111...11 to 000...00) from the ideal VIN(+) voltage,
which is (VIN(–) – 0.5 LSB) when operating in the bipolar mode.
Gain ErrorThe first code transition should occur at an analog value
0.5LSB above negative full scale. The last code transition
should occur for an analog value 1.5 LSB below the nominal
full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio (SNR)SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all of the nonfundamental signals up to
half the output data rate (fO/2), excluding dc. The ADC is
evaluated by applying a low noise, low distortion sine wave
signal to the input pins. By generating a Fast Fourier Trans-
form (FFT) plot, the SNR data can then be obtained from the
output spectrum.
Total Harmonic Distortion (THD)THD is the ratio of the rms sum of the harmonics to the rms
value of the fundamental. THD is defined as
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through
sixth harmonics.
Spurious Free Dynamic Range (SFDR)Defined as the difference, in dB, between the peak spurious or
harmonic component in the ADC output spectrum (up to
fO/2 and excluding dc) and the rms value of the fundamental.
Normally, the value of this specification will be determined by
the largest harmonic in the output spectrum of the FFT. For
input signals whose second harmonics occur in the stop band
region of the digital filter, the spur in the noise floor limits
the SFDR.
Settling Time and Group DelayThe settling time of a digital filter is dependent on the amount
of decimation employed and the number of filter taps used in
the filter design and is calculated as follows:
The settling time for each filter stage should be calculated
separately and then added to get the total filter settling time.
Group delay is half the settling time.
AD7725–Typical Performance Characteristics
PERFORMANCE PLOTSThe following typical plots are generated using the digital filter shown in Figure 1.
(AVDD = DVDD, TA = 25�C, CLKIN = 9.6 MHz, External Reference = 2.5 V, unless otherwise noted.)
TPC 1.SNR, THD, and SFDR vs. Analog Input
Level Relative to Full Scale
TPC 2.SNR, THD, and SFDR vs. Sampling Frequency
TPC 4.Histogram of Output Codes for a DC Input
TPC 5.16k Point FFT
