AD7724AST Fast Delivery |IC PHOENIX CO.,LIMITED

AD7724AST ,Dual CMOS ModulatorsSPECIFICATIONS When Tested with Ideal FIR Filter as in Figure 1Bipolar Mode BIP = V , V = 2.5 V, VI ..
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AD7724AST
Dual CMOS Modulators
REV. A
Dual CMOS S-D Modulators
FUNCTIONAL BLOCK DIAGRAM
FEATURES
13 MHz Master Clock Frequency
0 V to +2.5 V or 61.25 V Input Range
Single Bit Output Stream
90 dB Dynamic Range
Power Supplies
AVDD, DVDD: 5 V␣6 5%
DVDD1: 3 V 6 5%
Logic Outputs 3 V/5 V Compatible
On-Chip 2.5 V Voltage Reference
48-Lead LQFP
GENERAL DESCRIPTION
This device consists of two seventh order sigma-delta modula-
tors. Each modulator converts its analog input signal into a high
speed 1-bit data stream. The part operates from a 5 V power
supply and accepts a differential input range of 0 V to +2.5 V or1.25 V centered about a common-mode bias. The analog inputs
are continuously sampled by the analog modulators, eliminating
the need for external sample-and-hold circuitry. The input infor-
mation is contained in the output stream as a density of ones.
The original information can be digitally reconstructed with an
appropriate digital filter.
The part provides an accurate on-chip 2.5 V reference for each
modulator. A reference input/output function is provided to
allow either the internal reference or an external system refer-
ence to be used as the reference source for the modulator.
The device is offered in a 48-lead LQFP package and designed
to operate from –40°C to +85°C.
AD7724–SPECIFICATIONS1(AVDD = 5 V 6 5%; DVDD = 5 V 6 5%, DVDD1 = 3 V 6 5%; AGND = DGND = 0 V,
fMCLK = 13 MHz ac-coupled sine wave, REF2A = REF2B␣=␣2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
REFERENCE INPUTS
DYNAMIC SPECIFICATIONS
CLOCK
AD7724
NOTESOperating temperature range is as follows:␣A Version: –40°C to +85°C.Gain Error excludes reference error. The modulator gain is calibrated wrt the voltage on the REF2 pin.Measurement Bandwidth = 0.5 · fMCLK; Input Level = –0.05 dB.When a square wave clock is used, the dynamic specifications will degrade by 1 dB typically.
Specifications subject to change without notice.
BIT STREAM
BANDWIDTH = 94.25kHz
TRANSITION = 304.687kHz
ATTENUATION = 120dB
COEFFICIENTS = 384
16-BIT
OUTPUT
BANDWIDTH = 94.25kHz
TRANSITION = 108.874kHz
ATTENUATION = 90dB
COEFFICIENTS = 151
Figure 1.Digital Filter (Consists of Two FIR Filters). This Filter is implemented on the AD7722.
AD7724
TIMING CHARACTERISTICS
NOTE
Guaranteed by design.
OUTPUT
PIN
IOH
200mA
1.6V
Figure 2.Load Circuit for Access Time and Bus Relinquish Time
SCLK (O)
DATA (O)
NOTE:
O SIGNIFIES AN OUTPUT
Figure 3.Data Timing
MCLK (I)
RESET (I)
DVAL (O)
NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT
Figure 4.RESET Timing
(AVDD = 5V 6 5%; DVDD = 5 V 6 5%; DVDD1 = 3 V 6 5%; AGND = DGND = 0V, REF2A =
REF2B = 2.5 V, unless otherwise noted)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7724 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Inputs to DGND . . . . . . . . –0.3 V to DVDD + 0.3 V
Digital Outputs to DGND . . . . . . . –0.3 V to DVDD + 0.3 V
VIN(+), VIN(–) to AGND . . . . . . . –0.3 V to AVDD + 0.3 V
REF1 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
REF2 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°CJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
AVDD
AGND
BVIN(–)
BVIN(+)
AGND
AVDD
AVDD
AGND
AVIN(–)
AVIN(+)
AGND
AVDD
NC = NO CONNECT
STBY
MZERO
RESET
BIP
XTAL_OFFNCNCAGNDREF2AAGNDREF1AVDDNCREF2BAGNDNCNC
XTAL1
XTAL1/MCLK
DVDDDGNDDGND
ADATABDATA
SCLK
DVDD1
DVAL
ORDERING GUIDE
AD7724
PIN FUNCTION DESCRIPTIONS
AGND
AVIN(–), AVIN(+)
TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7724
[FIGURE 1])
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with bipolar zero), a point 0.5 LSB below the first code
transition (100␣.␣.␣.␣00 to 100␣.␣.␣.␣01 in bipolar mode and
000␣.␣.␣.␣00 to 000␣.␣.␣.␣01 in unipolar mode) and full scale, a
point 0.5 LSB above the last code transition (011␣.␣.␣.␣10 to
011␣.␣.␣.␣11 in bipolar mode and 111␣.␣.␣.␣10 to 111␣.␣.␣.␣11 in
unipolar mode). The error is expressed in LSBs.
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common–mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal VIN(+) voltage which is (VIN(–) + 0.5 LSB)
when operating in the unipolar mode.
Bipolar Offset Error
This is the deviation of the midscale transition (111␣.␣.␣.␣11
to 000␣.␣.␣.␣00) from the ideal VIN(+) voltage which is (VIN(–)
–0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above minus full scale. The last code transition should occur for
an analog value 1 1/2 LSB below the nominal full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Signal-to-(Noise + Distortion)
Signal-to-(Noise + Distortion) is the measured signal-to-noise
plus distortion ratio at the output of the ADC. The signal is the
rms magnitude of the fundamental. Noise plus distortion is the
rms sum of all of the nonfundamental signals and harmonics up
to half the Output Data Rate (fO/2), excluding dc. Signal-to-
(Noise + Distortion) is dependent on the number of quantiza-
tion levels used in the digitization process; the more levels, the
smaller the quantization noise. The theoretical Signal-to-(Noise
+ Distortion) ratio for a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
where N is the number of bits.
Total Harmonic Distortion
THD is the ratio of the rms sum of harmonics to the rms value
of the fundamental. THD is defined as
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
Spurious Free Dynamic Range
Spurious free dynamic range is the difference, in dB, between
the peak spurious or harmonic component in the ADC output
spectrum (up to fO/2 and excluding dc) and the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the output spectrum of
the FFT. For input signals whose second harmonics occur in
the stop band region of the digital filter, a spur in the noise floor
limits the SFDR.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).

Partno	Mfg	Dc	Qty	Available	Descript
AD7724AST	ADI	N/a	169	avai	Dual CMOS Modulators