AD7723BS Fast Delivery |IC PHOENIX CO.,LIMITED

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AD7723BS
16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC
REV.0
16-Bit, 1.2 MSPS
CMOS, Sigma-Delta ADC
FUNCTIONAL BLOCK DIAGRAM
AGND
AVDD
DGND
VIN(+)
VIN(–)
REF2
XTAL
CLKIN
MODE 1
STBY
SYNC
CFMT/RD
DGND/DRDY
DGND/
DB1
DOE/
DB4
SFMT/
DB5
FSI/
DB6
SCO/
DB7
DGND/
DB2
DGND/
DB3
SDO/
DB8
DGND/DB0
DVDD/CS
MODE 2
HALF_PWR
UNI
DGND/DB14
DGND/DB15
SCR/DB13
SLDR/DB12
SLP/DB11
TSI/DB10
FSO/DB9
XTAL_OFFREF1
DVDD
FEATURES
16-Bit Sigma-Delta ADC
1.2 MSPS Output Word Rate
32/16 3 Oversampling Ratio
Low-Pass and Band-Pass Digital Filter
Linear Phase
On-Chip 2.5 V Voltage Reference
Standby Mode
Flexible Parallel or Serial Interface
Crystal Oscillator
Single +5 V Supply
GENERAL DESCRIPTION
The AD7723 is a complete 16-bit, sigma-delta ADC. The part
operates from a +5␣V supply. The analog input is continuously
sampled, eliminating the need for an external sample-and-hold.
The modulator output is processed by a finite impulse response
(FIR) digital filter. The on-chip filtering combined with a high
oversampling ratio reduces the external antialias requirements
to first order in most cases. The digital filter frequency response
can be programmed to be either low pass or band pass.
The AD7723 provides 16-bit performance for input bandwidths
up to 460␣kHz at an output word rate up to 1.2 MHz. The
sample rate, filter corner frequencies and output word rate are
set by the crystal oscillator or external clock frequency.
Data can be read from the device in either serial or parallel
format. A stereo mode allows data from two devices to share a
single serial data line. All interface modes offer easy, high speed
connections to modern digital signal processors.
The part provides an on-chip 2.5␣V reference. Alternatively, an
external reference can be used.
A power-down mode reduces the idle power consumption to
200μW.
The AD7723 is available in a 44-lead PQFP package and is
specified over the industrial temperature range from –40°C to
+85°C.
Two input modes are provided, allowing both unipolar and
bipolar input ranges.
AD7723–SPECIFICATIONS1
(AVDD = DVDD = +5 V 6 5%; AGND = AGND1 = AGND2 = DGND = 0 V;
fCLKIN = 19.2 MHz; REF2 = 2.5 V; TA = TMIN to TMAX; unless otherwise noted)
AD7723
CLOCK
REFERENCE
LOGIC OUTPUTS
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2Typical values for SNR apply for parts soldered directly to a printed circuit board ground plane.
3Dynamic specifications apply for input signal frequencies from dc to 0.0240 × fCLKIN in decimate by 16 mode and from dc to 0.0120 × fCLKIN in decimate by 32 mode.
4When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 μF decoupling capacitor between REF2 and
AGND2. At frequencies below 10 kHz, THD degrades to 84 dB and SFDR degrades to 86 dB.
5Gain Error excludes Reference Error.
6CLKIN and digital inputs static and equal to 0 or DVDD.
Specifications subject to change without notice.
AD7723
(AVDD = DVDD = +5 V 6 5%; AGND = AGND1 = DGND = 0 V; fCLKIN = 19.2 MHz; CL = 50 pF; SFMT =
Logic Low or High, CFMT = Logic Low or High; TA = TMIN to TMAX unless otherwise noted)TIMING SPECIFICATIONS
NOTES
1FSO pulses are gated by the release of FSI (going low).
2Guaranteed by design.
3Frame Sync is initiated on the falling edge of CLKIN.
Specifications subject to change without notice.
Figure 1.Load Circuit for Timing Specifications
CLKIN
FSI
SCOt5
Figure 2.Serial Mode Timing for Clock Input, Frame Sync Input and Serial Clock Output
CLKIN
FSI
(SFMT = 1)
SCO
(CFMT = 0)
FSO
(SFMT = 0)
FSO
(SFMT = 1)
SDO
Figure 3.Serial Mode 1.Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output
(Refer to Table I for Control Inputs, TSI = DOE)
t11
t13
CLKIN
FSI
SCO
(CFMT = 0)
FSO
AD7723
t11
t13
CLKIN
FSI
SCO
(CFMT = 0)
FSO
SDO
Figure 5.Serial Mode 3.Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output
(Refer to Table I for Control Inputs, TSI = DOE)
Table I.Serial Interface (Mode1 = 0, Mode2 = 0)
Table II.Parallel Interface
t16
DOE
SDO
Figure 6.Serial Mode Timing for Data Output Enable and Serial Data Output
CLKIN
DRDY
DB0–DB15
Figure 7a.Parallel Mode Read Timing, CS and RD Tied Logic Low
CLKIN
DRDY
RD/CS
DB0–DB15
Figure 7b.Parallel Mode Read Timing, CS = RD
Figure 8.SYNC Timing
AD7723
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7723 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD, AVDD1 to AGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD, AVDD1 to DVDD . . . . . . . . . . . . . . . . . . . –1 V to +1 V
AGND, AGND1 to DGND . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Inputs to DGND . . . . . . . . . –0.3 V to DVDD + 0.3 V
Digital Outputs to DGND . . . . . . . . –0.3 V to DVDD + 0.3 V
VIN(+), VIN(–) to AGND . . . . . . . . –0.3 V to AVDD + 0.3 V
REF1 to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
REF2 to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
PIN CONFIGURATION
44-Lead PQFP Package
PIN FUNCTION DESCRIPTIONS
AGND1
AVDD
AGND
AGND2
DVDD
DGND
REF1
REF2
VIN(+)
VIN(–)
UNI
CLKIN
XTAL
XTAL_OFF
MODE1/2
HALF_PWR
SYNC
AD7723
PARALLEL MODE PIN FUNCTION DESCRIPTIONS
CFMT/RD
DGND/DRDY
DGND/DB15
DGND/DB14
SCR/DB13
SLDR/DB12
SLP/DB11
TSI/DB10
FSO/DB9
SDO/DB8
SCO/DB7
FSI/DB6
SFMT/DB5
DOE/DB4
DGND/DB3
DGND/DB2
DGND/DB1
SERIAL MODE PIN FUNCTION DESCRIPTIONS
AD7723
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all of the nonfundamental signals up to
half the output data rate (FO/2), excluding dc. The ADC is
evaluated by applying a low noise, low distortion sine wave
signal to the input pins. By generating a Fast Fourier Transform
(FFT) plot, the SNR data can then be obtained from the out-
put spectrum.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the rms
value of the fundamental. THD is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through
sixth harmonics. The THD is also derived from the FFT plot of
the ADC output spectrum.
Spurious Free Dynamic Range (SFDR)
Defined as the difference, in dB, between the peak spurious or
harmonic component in the ADC output spectrum (up to FO/2
and excluding dc) and the rms value of the fundamental.
Normally, the value of this specification will be determined by
the largest harmonic in the output spectrum of the FFT. For
input signals whose second harmonics occur in the stop band
region of the digital filter, the spur in the noise floor limits the
SFDR.
Passband Ripple
The frequency response variation of the AD7723 in the defined
passband frequency range.
Passband Frequency
The frequency up to which the frequency response variation is
within the passband ripple specification.
Cutoff Frequency
The frequency below which the AD7723’s frequency response
will not have more than 3 dB of attenuation.
Stopband Frequency
The frequency above which the AD7723’s frequency response
will be within its stopband attenuation.
Stopband Attenuation
The AD7723’s frequency response will not have less than 90 dB
of attenuation in the stated frequency band.
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are minus full scale, a point
0.5 LSB below the first code transition (100...00 to 100...01
in bipolar mode, 000...00 to 000...01 in unipolar mode)
and plus full scale, a point 0.5 LSB above the last code transi-
tion (011...10 to 011...11 in bipolar mode, 111...10 to
111...11 in unipolar mode). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and the ideal 1LSB
change between two adjacent codes in the ADC.
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common–mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
(10...000 to 10...001) from the ideal differential voltage
(VIN(+) – VIN(–)+ 0.5 LSB) when operating in the unipolar
mode.
Bipolar Offset Error
This is the deviation of the midscale transition code (111...11
to 000...00) from the ideal differential voltage (VIN(+) –
VIN(–) – 0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value 1/2LSB
above –full scale. The last transition should occur for an analog
value 1 1/2 LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.

Partno	Mfg	Dc	Qty	Available	Descript
AD7723BS	AD	N/a	25	avai	16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC