AD7722AS Fast Delivery |IC PHOENIX CO.,LIMITED

AD7722AS ,16-Bit, 195 kSPS CMOS, Sigma-Delta ADCSPECIFICATIONSBipolar Mode, UNI = V V = 2.5 V, V (+) = V (–) =1.25 V pk-pkINH CM IN INor, V (–) =1. ..
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AD7722AS
16-Bit, 195 kSPS CMOS, Sigma-Delta ADC
REV.0
16-Bit, 195 kSPS
CMOS, Sigma-Delta ADC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
16-Bit Sigma-Delta ADC
643 Oversampling Ratio
Up to 220 kSPS Output Word Rate
Low-Pass, Linear Phase Digital Filter
Inherently Monotonic
On-Chip 2.5 V Voltage Reference
Single Supply +5 V
High Speed Parallel or Serial Interface
GENERAL DESCRIPTION
The AD7722 is a complete low power, 16-bit, sigma-delta
ADC. The part operates from a +5 V supply and accepts a
differential input voltage range of 0 V to +2.5 V or ±1.25 V
centered around a common-mode bias. The AD7722 provides
16-bit performance for input bandwidths up to 90.625 kHz.
The part provides data at an output word rate of 195.3 kHz.
The analog input is continuously sampled by an analog modula-
tor eliminating the need for external sample-and-hold circuitry.
The modulator output is processed by two Finite Impulse
Response (FIR) digital filters in series. The on-chip filtering
reduces the external antialias requirements to first order, in
most cases. The group delay for the filter is 215.5 μs, while the
settling time for a step input is 431 μs. The sample rate, filter
corner frequency, and output word rate are set by an external
clock that is nominally 12.5 MHz.
Use of a single bit DAC in the modulator guarantees excellent
linearity and dc accuracy. Endpoint accuracy is ensured by on-
chip calibration. This calibration procedure minimizes the zero-
scale and full-scale errors.
Conversion data is provided at the output register through a
flexible serial port or a parallel port. This offers 3-wire, high
speed interfacing to digital signal processors. The serial interface
operates in an internal clocking (master) mode, whereby an
internal serial data clock and framing pulse are device outputs.
Additionally, two AD7722s can be configured with the serial
data outputs connected together. Each converter alternately
transmits its conversion data on a shared serial data line.
The part provides an accurate on-chip 2.5 V reference. A
reference input/output function is provided to allow either the
internal reference or an external system reference to be used as
the reference source for the part.
The AD7722 is available in a 44-pin PQFP package and is
specified over the industrial temperature range from –40°C to
+85°C.
AD7722–SPECIFICATIONS1(AVDD = AVDD1 = +5 V 6 5%; DVDD = +5 V 6 5%; AGND = AGND1 = DGND = 0 V;
UNI = Logic Low or High; fCLKLIN = 12.5 MHz; FS = 195.3 kSPS; REF2 = +2.5 V; TA = TMIN to TMAX; unless otherwise noted)
AD7722
NOTESOperating temperature range is as follows : A Version ; –40°C to +85°C.Measurement Bandwidth = 0.5 × FS; Input Level = –0.05 dB.TA = +25°C to +85°C/TA = TMIN to TMAX.Applies after calibration at temperature of interest.Gain Error excludes reference error. The ADC gain is calibrated w.r.t. the voltage on the REF2 pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to 7 V
AVDD, AVDD1 to AGND . . . . . . . . . . . . . . . . . .–0.3 V to 7 V
AVDD, AVDD1 to DVDD . . . . . . . . . . . . . . . . . . .–1 V to +1 V
AGND, AGND1 to DGND . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital Inputs to DGND . . . . . . . . . .–0.3 V to DVDD + 0.3 V
Digital Outputs to DGND . . . . . . . . .–0.3 V to DVDD + 0.3 V
VIN(+), VIN(–) to AGND . . . . . . . . . .–0.3 V to AVDD + 0.3 V
REF1 to AGND . . . . . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
REF2 to AGND . . . . . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . . .±0.3 V
Operating Temperature Range . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
ORDERING GUIDE
Figure 1.Load Circuit for Timing Specifications
AD7722
TIMING SPECIFICATIONS
NOTESGuaranteed by design.Frame Sync is initiated on falling edge of CLKIN.With RD synchronous to CLKIN t22, can be reduced up to 1 tCLK.
(AVDD= +5 V 6 5%, DVDD = +5 V 6 5%, AGND = DGND = 0 V, CL = 50 pF, TA = TMIN to TMAX,
fCLKIN = 12.5 MHz, SFMT = Logic Low or High, CFMT = Logic Low or High)
CLKIN
SCO
(CFMT = 0)
FSO
(SFMT = 0)
SCO
Figure 2a.Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
CLKIN
SCO
(CFMT = 0)
FSO
(SFMT = 1)
SCOLOW FOR 16 SCO CYCLES
Figure 2b.Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
CLKIN
FSI
SCO
Figure 3.Serial Mode Timing for Clock Input, Frame Sync Input and Serial Clock Output
CLKIND13
FSI
SCO
FSO
SDO
SCO
FSO
SDO
SFMT = LOGIC
LOW(0)
SFMT = LOGIC
HIGH(1)
AD7722
t15
DOE
SDO
Figure 5.Serial Mode Timing for Data Output Enable and Serial Data Output (TSI = Logic Low)
t20
DB0 – DB15
VALID DATA
DRDY
Figure 6.Parallel Mode Read Timing
CLKIN
DVAL
DRDY
SYNC, RESET
Figure 7.SYNC and RESET Timing, Serial and Parallel Mode
CLKIN
DVAL
DRDY
CAL
Figure 8.Calibration Timing, Serial and Parallel Mode
PIN FUNCTION DESCRIPTION
AGND1
AVDD
DGND
REF1
REF2
VIN(+)
VIN(–)
AD7722
PIN CONFIGURATION
44-Pin PQFP (S-44)
DGND/DB13
DGND/DB14
DGND/DB15
SYNC
DGND
CAL
AGND
AGND
REF2
AVDD
DGND/DB2
DGND/DB1
DGND/DB0
CFMT/DRDY
DVAL/RD
DGND
UNI
P/S
AGND
AGND1
CLKIN
TSI/DB3
DOE/DB4SFMT/DB5FSI/DB6SCO/DB7DV
SDO/DB8FSO/DB9DGND/DB10DGND/DB11DGND/DB12
XTAL
AGND
DD1
AGNDVIN(–)
RESET
VIN(+)AGND
AGND
REF1
PARALLEL MODE PIN FUNCTION DESCRIPTION
SERIAL MODE PIN FUNCTION DESCRIPTION
CFMT/DRDY
AD7722
TERMINOLOGY
Signal-to-Noise Plus Distortion Ratio (S/(N+D))
S/(N+D) is the measured signal-to-noise plus distortion ratio at
the output of the ADC. The signal is the rms magnitude of the
fundamental. Noise plus distortion is the rms sum of all of the
nonfundamental signals and harmonics to half the sampling
rate (FCLKIN/128), excluding dc. The ADC is evaluated by
applying a low noise, low distortion sine wave signal to the
input pins. By generating a Fast Fourier Transform (FFT)
plot, the S/(N+D) data can then be obtained from the output
spectrum.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the rms
value of the fundamental. THD is defined as:
THD=20log
SQRTV22+V3+V42+V52+V62()
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through
sixth harmonics. The THD is also derived from the FFT plot
of the ADC output spectrum.
Spurious Free Dynamic Range (SFDR)
Defined as the difference, in dB, between the peak spurious or
harmonic component in the ADC output spectrum (up to
FCLKIN/128 and excluding dc) and the rms value of the funda-
mental. Normally, the value of this specification will be deter-
mined by the largest harmonic in the output spectrum of the
FFT. For input signals whose second harmonics occur in the
stop band region of the digital filter, a spur in the noise floor
limits the SFDR.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamental expressed in dB.
Pass-Band Ripple
The frequency response variation of the AD7722 in the defined
pass-band frequency range.
Pass-Band Frequency
The frequency up to which the frequency response variation is
within the pass-band ripple specification.
Cutoff Frequency
The frequency below which the AD7722’s frequency response
will not have more than 3 dB of attenuation.
Stop-Band Frequency
The frequency above which the AD7722’s frequency response
will be within its stop-band attenuation.
Stop-Band Attenuation
The AD7722’s frequency response will not have less than 90 dB
of attenuation in the stated frequency band.
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are minus full scale, a point
0.5 LSB below the first code transition (100 . . . 00 to 100 . . .
01 in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode)
and plus full scale, a point 0.5 LSB above the last code transi-
tion (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to
111 . . . 11 in unipolar mode). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between two adjacent codes in the ADC.
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common-mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
(00 . . . 000 to 00 . . . 001) from the ideal differential voltage
(VIN(+) – VIN(–)+ 0.5 LSB) when operating in the unipolar
mode.
Bipolar Offset Error
This is the deviation of the midscale transition code (111 . . . 11
to 000 . . . 00) from the ideal differential voltage (VIN(+) –
VIN(–) – 0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value
1/2 LSB above –full scale. The last transition should occur for
an analog value 1 1/2 LSB below the nominal full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
(AVDD = DVDD = 5.0 V, TA = +258C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode; VIN(+) = 0 V to 2.5 V, VIN(–) = 1.25 V unless otherwise noted)
100–40
Figure 9.
Analog Input Level
–110
Figure 12.
Input Frequency
TEMPERATURE – °C
–98
Figure 15.THD vs. Temperature
CODES
n–3n–2n+3n–1nn+1n+2
Figure 16.Histogram of Output
Codes with DC InputSNR vs. Temperature
Figure 17.Differential Nonlinearity
CODE
INL ERROR – LSB
0.4
Figure 18.Integral Nonlinearity Error
(AVDD = DVDD = 5.0 V, TA = +258C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode; VIN(+) = 0 V to 2.5 V, VIN(–) = 1.25 V unless otherwise noted)AD7722–Typical Characteristics
Figure 21.Power Consumption vs.
CLKIN Frequency
0E+010E+320E+330E+340E+350E+360E+370E+380E+398E+3
90E+3
Figure 19.16K Point FFT
0E+010E+320E+330E+340E+350E+360E+370E+380E+396E+390E+3
Figure 20.16K Point FFT
Figure 22.16K Point FFT
0E+010E+320E+330E+340E+350E+360E+370E+380E+396E+3
90E+3
Figure 23.16K Point FFT

Partno	Mfg	Dc	Qty	Available	Descript
AD7722AS		N/a	32	avai	16-Bit, 195 kSPS CMOS, Sigma-Delta ADC