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AD7721AN-AD7721AR
CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC
REV.A
CMOS 16-Bit,
468.75 kHz, Sigma-Delta ADCUse of a single bit DAC in the modulator guarantees excellent
linearity and dc accuracy. Endpoint accuracy is ensured by on-
chip calibration of offset and gain. This calibration procedure
minimizes the part’s zero-scale and full-scale errors.
The output data is accessed from the output register through a
serial or parallel port. This offers easy, high speed interfacing to
modern microcontrollers and digital signal processors. The
serial interface operates in internal clocking (master) mode, the
AD7721 providing the serial clock.
CMOS construction ensures low power dissipation while a
power-down mode reduces the power consumption to only
100μW.
GENERAL DESCRIPTIONThe AD7721 is a complete low power, 12-/16-bit, sigma-delta
ADC. The part operates from a +5V supply and accepts a
differential input of 0 V to 2.5 V or ±1.25 V. The analog input
is continuously sampled by an analog modulator at twice the
clock frequency eliminating the need for external sample-and-
hold circuitry. The modulator output is processed by two finite
impulse response (FIR) digital filters in series. The on-chip
filtering reduces the external antialias requirements to first order
in most cases. Settling time for a step input is 97.07μs while
the group delay for the filter is 48.53μs when the master clock
equals 15MHz.
The AD7721 can be operated with input bandwidths up to
229.2kHz. The corresponding output word rate is 468.75kHz.
The part can be operated with lower clock frequencies also.
The sample rate, filter corner frequency and output word rate
will be reduced also, as these are proportional to the external
clock frequency. The maximum clock frequencies in parallel
mode and serial mode are 10MHz and 15MHz respectively.
FEATURES
16-Bit Sigma-Delta ADC
468.75kHz Output Word Rate (OWR)
No Missing Codes
Low-Pass Digital Filter
High Speed Serial Interface
Linear Phase
229.2kHz Input Bandwidth
Power Supplies: AVDD, DVDD: +5 V6
5%
Standby Mode (70mW)
Parallel Mode (12-Bit/312.5 kHz OWR)
FUNCTIONAL BLOCK DIAGRAM
VIN1
AVDDDVDDAGND
DGND
DB8
SDATA/DB11
DB9
DRDY
RFS/DB10
DB4
STBY/DB0
CAL/DB1
CLK
VIN2
DB3
DVAL/SYNC
UNI/DB2
REFINDSUBST
DGND
SYNC/
DB5
DB6SCLK/
DB7
AGND
AD7721–SPECIFICATIONS1ANALOG INPUTS
DYNAMIC SPECIFICATIONS
CLOCK
NOTESOperating temperature range is as follows:A Version: –40°C to +85°C; S Version: –55°C to +125°C.
(AVDD = +5 V 6 5%; DVDD = +5 V 6 5%; AGND = DGND = 0 V,
fCLK = 15 MHz, REFIN=+2.5 V; TA = TMIN to TMAX, unless otherwise noted)
SPECIFICATIONS1NOTESOperating temperature range is as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C.Applies after calibration at temperature of interest.Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin.
Specifications subject to change without notice.
(AVDD = +5 V 6 5%; DVDD = +5 V 6 5%; AGND = DGND = 0 V, fCLK = 10 MHz,
REFIN=+2.5 V; TA = TMIN to TMAX, unless otherwise noted)AD7721
AD7721
TIMING CHARACTERISTICS1, 2tCLK HI
tCLK HI
Read Operation
t10
t12
NOTES
The timing is measured with a load of 50 pF on SCLK and DRDY. SCLK can be operated with a load capacitance of 50 pF maximum.Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.All digital outputs are timed with the load circuit below and, except for t2, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last.The AD7721 is production tested with fCLK at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character-
ization to operate with CLK frequencies down to 100 kHz.t2 is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V.t8 and t15 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus
relinquish time of the part and, as such, is independent of external bus loading capacitance.
Figure 1.Load Circuit for Access Time and Bus Relinquish Time
(AVDD= +5 V 6 5%; DVDD= +5 V 6 5%; AGND = DGND = 0 V, REFIN=+2.5 V
unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise stated)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ±10 mA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Plastic Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . +260°C
Cerdip Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 51°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . +300°C
SOIC Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 72°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latchup.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*N = Plastic DIP; R = 0.3" Small Outline IC (SOIC); Q = Cerdip.
PIN CONFIGURATION
AD7721
PIN FUNCTION DESCRIPTIONS
Parallel Mode OnlyControl functions such as CAL, UNI and STBY, which are available as pins in serial mode, are available as bits in parallel mode.
Table I lists the contents of the control register onboard the AD7721. This register is written to in parallel mode using the WR pin.
Table I.Function of Control Register Bits
AD7721
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale (not to be con-
fused with bipolar zero), a point 0.5 LSB below the first code
transition (100...00 to 100...01 in bipolar mode and
000...00 to 000...01 in unipolar mode) and full scale, a point
0.5 LSB above the last code transition (011...10 to 011...11 in
bipolar mode and 111...10 to 111...11 in unipolar mode). The
error is expressed in LSBs.
Differential NonlinearityThis is the difference between the measured and the ideal 1LSB
change between two adjacent codes in the ADC.
Common Mode Rejection RatioThe ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common-mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset ErrorUnipolar offset error is the deviation of the first code transition
from the ideal VIN1 voltage which is (VIN2 + 0.5 LSB) when
operating in the unipolar mode.
Bipolar Offset ErrorThis is the deviation of the midscale transition (111...11
to 000...00) from the ideal VIN1 voltage which is (VIN2 –
0.5 LSB) when operating in the bipolar mode.
Unipolar Full-Scale ErrorUnipolar full-scale error is the deviation of the last code transition
(111...10 to 111...11) from the ideal VIN1 voltage which is
(VIN2 + VREFIN – 3/2 LSBs).
Bipolar Full-Scale ErrorThe bipolar full-scale error refers to the positive full-scale error and
the negative full-scale error. The positive full-scale error is the
deviation of the last code transition (011...10 to 011...11) from
the ideal VIN1 voltage which is (VIN2 + VREFIN/2 – 3/2 LSB).
The negative full-scale error is the deviation of the first code transi-
tion (100...00 to 100...01) from the ideal VIN1 voltage which
is (VIN2 – VREFIN/2 + 0.5 LSB).
Signal to (Noise + Distortion)Signal to (Noise + Distortion) is measured signal to noise at the
output of the ADC. The signal is the rms magnitude of the funda-
mental. Noise is the rms sum of all the nonfundamental signals up
to half the sampling frequency (fCLK/2) but excluding the dc com-
ponent. Signal to (Noise + Distortion) is dependent on the num-
ber of quantization levels used in the digitization process; the more
levels, the smaller the quantization noise. The theoretical Signal to
(Noise + Distortion) ratio for a sine wave input is given by
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
where N is the number of bits. Thus, for an ideal 12-bit converter,
Signal to (Noise + Distortion) = 74 dB.
Total Harmonic DistortionTotal Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
USING THE AD7721
ADC Differential InputsThe AD7721 uses differential inputs to provide common-mode
noise rejection. In the bipolar mode configuration, the analog
input range is ±1.25 V. The designed code transitions occur
midway between successive integer LSB values. The output
code is 2s complement binary with 1 LSB = 0.61 mV in paral-
lel mode and 38 μV in serial mode. The ideal input/output
transfer function is illustrated in Figure 2.
In the unipolar mode, the analog input range is 0 V to 2.5 V.
Again, the designed code transitions occur midway between suc-
cessive integer LSB values. The output code is straight binary with
1 LSB = 0.61 mV in parallel mode and 38 μV in serial mode. The
ideal input/output transfer function is shown in Figure 3.
DIFFERENTIAL INPUT VOLTAGE (VIN1–VIN2)
OUTPUT
CODEFigure 2.AD7721 Bipolar Mode Transfer Function
OUTPUT
CODE
000...011
